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https://github.com/c64scene-ar/llvm-6502.git
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807360ab08
Handle the poor codegen for i64/x86xmm->v2i64 (%mm -> %xmm) moves. Instead of using stack store/load pair to do the job, use scalar_to_vector directly, which in the MMX case can use movq2dq. This was the current behavior prior to improvements for vector legalization of extloads in r213897. This commit fixes the regression and as a side-effect also remove some unnecessary shuffles. In the new attached testcase, we go from: pshufw $-18, (%rdi), %mm0 movq %mm0, -8(%rsp) movq -8(%rsp), %xmm0 pshufd $-44, %xmm0, %xmm0 movd %xmm0, %eax ... To: pshufw $-18, (%rdi), %mm0 movq2dq %mm0, %xmm0 movd %xmm0, %eax ... Differential Revision: http://reviews.llvm.org/D7126 rdar://problem/19413324 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226953 91177308-0d34-0410-b5e6-96231b3b80d8
190 lines
4.5 KiB
LLVM
190 lines
4.5 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -mattr=+sse2 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=core2 -mattr=+sse2 -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE
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define double @test1(double %A) {
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%1 = bitcast double %A to <2 x i32>
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%add = add <2 x i32> %1, <i32 3, i32 5>
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%2 = bitcast <2 x i32> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test1 into a
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; single paddd instruction. At the moment we produce the sequence
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; pshufd+paddq+pshufd. This is fixed with the widening legalization.
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;
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; CHECK-LABEL: test1
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: paddd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test1
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; CHECK-WIDE-NOT: movsd
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; CHECK-WIDE: paddd
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; CHECK-WIDE-NEXT: ret
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define double @test2(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%add = add <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %add to double
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ret double %3
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: movsd
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; CHECK: paddd
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test2
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; CHECK-WIDE-NOT: movsd
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; CHECK-WIDE: paddd
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; CHECK-WIDE-NEXT: ret
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define i64 @test3(i64 %A) {
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%1 = bitcast i64 %A to <2 x float>
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%add = fadd <2 x float> %1, <float 3.0, float 5.0>
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%2 = bitcast <2 x float> %add to i64
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ret i64 %2
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: pshufd
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; CHECK: addps
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; CHECK-NOT: pshufd
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; CHECK: ret
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;
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; CHECK-WIDE-LABEL: test3
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; CHECK-WIDE-NOT: pshufd
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; CHECK-WIDE: addps
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; CHECK-WIDE-NOT: pshufd
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; CHECK-WIDE: ret
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define i64 @test4(i64 %A) {
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%1 = bitcast i64 %A to <2 x i32>
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%add = add <2 x i32> %1, <i32 3, i32 5>
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%2 = bitcast <2 x i32> %add to i64
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ret i64 %2
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}
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; FIXME: At the moment we still produce the sequence paddd+pshufd.
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; Ideally, we should fold that sequence into a single paddd. This is fixed with
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; the widening legalization.
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;
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; CHECK-LABEL: test4
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; CHECK: movd
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; CHECK-NOT: pshufd
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; CHECK-NEXT: paddd
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; CHECK-NEXT: pshufd
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; CHECK: ret
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;
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; CHECK-WIDE-LABEL: test4
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; CHECK-WIDE: movd %{{rdi|rcx}},
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; CHECK-WIDE-NEXT: paddd
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; CHECK-WIDE-NEXT: movd {{.*}}, %rax
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; CHECK-WIDE: ret
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define double @test5(double %A) {
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%1 = bitcast double %A to <2 x float>
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%add = fadd <2 x float> %1, <float 3.0, float 5.0>
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%2 = bitcast <2 x float> %add to double
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ret double %2
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}
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; CHECK-LABEL: test5
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; CHECK: addps
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test5
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; CHECK-WIDE: addps
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; CHECK-WIDE-NEXT: ret
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define double @test6(double %A) {
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%1 = bitcast double %A to <4 x i16>
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%add = add <4 x i16> %1, <i16 3, i16 4, i16 5, i16 6>
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%2 = bitcast <4 x i16> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test6 into a
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; single paddw instruction. This is fixed with the widening legalization.
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;
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; CHECK-LABEL: test6
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; CHECK-NOT: movsd
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; CHECK: punpcklwd
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; CHECK-NEXT: paddw
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test6
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; CHECK-WIDE-NOT: mov
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; CHECK-WIDE-NOT: punpcklwd
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; CHECK-WIDE: paddw
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; CHECK-WIDE-NEXT: ret
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define double @test7(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%add = add <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %add to double
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ret double %3
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: movsd
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; CHECK-NOT: punpcklwd
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; CHECK: paddw
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test7
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; CHECK-WIDE-NOT: movsd
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; CHECK-WIDE-NOT: punpcklwd
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; CHECK-WIDE: paddw
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; CHECK-WIDE-NEXT: ret
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define double @test8(double %A) {
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%1 = bitcast double %A to <8 x i8>
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%add = add <8 x i8> %1, <i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10>
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%2 = bitcast <8 x i8> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test8 into a
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; single paddb instruction. At the moment we produce the sequence
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; pshufd+paddw+pshufd. This is fixed with the widening legalization.
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;
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; CHECK-LABEL: test8
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; CHECK-NOT: movsd
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; CHECK: punpcklbw
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; CHECK-NEXT: paddb
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test8
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; CHECK-WIDE-NOT: movsd
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; CHECK-WIDE-NOT: punpcklbw
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; CHECK-WIDE: paddb
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; CHECK-WIDE-NEXT: ret
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define double @test9(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%add = add <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %add to double
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ret double %3
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: movsd
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; CHECK-NOT: punpcklbw
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; CHECK: paddb
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; CHECK-NEXT: ret
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;
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; CHECK-WIDE-LABEL: test9
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; CHECK-WIDE-NOT: movsd
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; CHECK-WIDE-NOT: punpcklbw
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; CHECK-WIDE: paddb
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; CHECK-WIDE-NEXT: ret
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