Jakob Stoklund Olesen ee27cac9fa Avoid high-latency false CPSR dependencies even for tMOVSi. ... The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-04 18:25:36 +00:00
..
AArch64	Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings	2013-03-26 18:56:54 +00:00
ARM	Avoid high-latency false CPSR dependencies even for tMOVSi.	2013-04-04 18:25:36 +00:00
CPP
Generic
Hexagon	Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.	2013-03-28 19:34:49 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze
Mips	[mips] Small update to the implementation of eh.return for Mips.	2013-04-02 23:02:07 +00:00
MSP430
NVPTX	[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.	2013-03-30 14:29:30 +00:00
PowerPC	Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.	2013-04-03 13:05:44 +00:00
R600	R600: Take export into account when computing cf address	2013-04-04 13:59:59 +00:00
SI
SPARC	Add SPARC v9 support for select on 64-bit compares.	2013-04-04 03:08:00 +00:00
Thumb	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
Thumb2
X86	Temporarily relax the WIN32 checks in the SRet test to fix the Atom D2700 bot	2013-04-03 12:17:15 +00:00
XCore