Ulrich Weigand 1a21909e98 [SystemZ] Add z13 vector facility and MC support ... This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-05 19:23:40 +00:00
..
insns-pcrel.txt
insns-z13-bad.txt	[SystemZ] Add z13 vector facility and MC support	2015-05-05 19:23:40 +00:00
insns-z13.txt	[SystemZ] Add z13 vector facility and MC support	2015-05-05 19:23:40 +00:00
insns.txt	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
invalid-regs.txt
lit.local.cfg
trunc-01.txt
trunc-02.txt
trunc-03.txt
unmapped.txt