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bcf81629b8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
2.1 KiB
TableGen
45 lines
2.1 KiB
TableGen
//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM v7 processors.
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//
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//===----------------------------------------------------------------------===//
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// Single issue pipeline so every itinerary starts with FU_Pipe0
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def V7Itineraries : ProcessorItineraries<[
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// single-cycle integer ALU
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InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
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// loads have an extra cycle of latency, but are fully pipelined
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InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
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// fully-pipelined stores
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InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>,
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// fp ALU is not pipelined
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InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0]>]>,
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// no delay slots, so the latency of a branch is unimportant
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>
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]>;
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// Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
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def CortexA8Itineraries : ProcessorItineraries<[
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// single-cycle integer ALU
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InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
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// loads have an extra cycle of latency, but are fully pipelined
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InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0]>]>,
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// fully-pipelined stores
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InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
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// fp ALU is not pipelined
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InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0, FU_Pipe1]>]>,
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// no delay slots, so the latency of a branch is unimportant
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>
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]>;
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