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https://github.com/c64scene-ar/llvm-6502.git
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9a3e49a1b3
Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
2.3 KiB
Makefile
58 lines
2.3 KiB
Makefile
##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file was developed by the LLVM research group and is distributed under
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# the University of Illinois Open Source License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = x86
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include $(LEVEL)/Makefile.common
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TARGET = X86
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
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X86GenIntelAsmWriter.inc
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TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
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$(SourceDir)/../Target.td
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$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register info implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td AT&T assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
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$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td Intel assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@
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#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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# @echo "Building $(TARGET).td instruction selector with tblgen"
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# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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clean::
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$(VERB) rm -f *.inc
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