mirror of
https://github.com/c64scene-ar/llvm-6502.git
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82865a10f8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101085 91177308-0d34-0410-b5e6-96231b3b80d8
439 lines
17 KiB
C++
439 lines
17 KiB
C++
//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower X86 MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MCInstLower.h"
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#include "X86AsmPrinter.h"
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#include "X86COFFMachineModuleInfo.h"
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#include "X86MCAsmInfo.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/Type.h"
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using namespace llvm;
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const X86Subtarget &X86MCInstLower::getSubtarget() const {
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return AsmPrinter.getSubtarget();
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}
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MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
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assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin");
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return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
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}
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MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
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const TargetLowering *TLI = AsmPrinter.TM.getTargetLowering();
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return static_cast<const X86TargetLowering*>(TLI)->
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getPICBaseSymbol(AsmPrinter.MF, Ctx);
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}
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/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
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/// operand to an MCSymbol.
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MCSymbol *X86MCInstLower::
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GetSymbolFromOperand(const MachineOperand &MO) const {
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assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
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SmallString<128> Name;
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if (!MO.isGlobal()) {
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assert(MO.isSymbol());
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Name += AsmPrinter.MAI->getGlobalPrefix();
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Name += MO.getSymbolName();
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} else {
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const GlobalValue *GV = MO.getGlobal();
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bool isImplicitlyPrivate = false;
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if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
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MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
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MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
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MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
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isImplicitlyPrivate = true;
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Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
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}
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// If the target flags on the operand changes the name of the symbol, do that
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// before we return the symbol.
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switch (MO.getTargetFlags()) {
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default: break;
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case X86II::MO_DLLIMPORT: {
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// Handle dllimport linkage.
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const char *Prefix = "__imp_";
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Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
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break;
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}
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case X86II::MO_DARWIN_NONLAZY:
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
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Name += "$non_lazy_ptr";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getGVStubEntry(Sym);
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if (StubSym.getPointer() == 0) {
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assert(MO.isGlobal() && "Extern symbol not handled yet");
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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}
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return Sym;
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}
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
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Name += "$non_lazy_ptr";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getHiddenGVStubEntry(Sym);
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if (StubSym.getPointer() == 0) {
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assert(MO.isGlobal() && "Extern symbol not handled yet");
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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}
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return Sym;
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}
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case X86II::MO_DARWIN_STUB: {
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Name += "$stub";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getFnStubEntry(Sym);
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if (StubSym.getPointer())
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return Sym;
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if (MO.isGlobal()) {
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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} else {
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Name.erase(Name.end()-5, Name.end());
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
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}
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return Sym;
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}
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}
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return Ctx.GetOrCreateSymbol(Name.str());
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}
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MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MCSymbol *Sym) const {
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// FIXME: We would like an efficient form for this, so we don't have to do a
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// lot of extra uniquing.
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const MCExpr *Expr = 0;
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MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
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switch (MO.getTargetFlags()) {
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default: llvm_unreachable("Unknown target flag on GV operand");
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case X86II::MO_NO_FLAG: // No flag.
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// These affect the name of the symbol, not any suffix.
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case X86II::MO_DARWIN_NONLAZY:
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case X86II::MO_DLLIMPORT:
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case X86II::MO_DARWIN_STUB:
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break;
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case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
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case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
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case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
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case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
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case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
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case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
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case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
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case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
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case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
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case X86II::MO_PIC_BASE_OFFSET:
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
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Expr = MCSymbolRefExpr::Create(Sym, Ctx);
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// Subtract the pic base.
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Expr = MCBinaryExpr::CreateSub(Expr,
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MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
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Ctx);
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if (MO.isJTI() && AsmPrinter.MAI->hasSetDirective()) {
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// If .set directive is supported, use it to reduce the number of
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// relocations the assembler will generate for differences between
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// local labels. This is only safe when the symbols are in the same
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// section so we are restricting it to jumptable references.
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MCSymbol *Label = Ctx.CreateTempSymbol();
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AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
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Expr = MCSymbolRefExpr::Create(Label, Ctx);
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}
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break;
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}
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if (Expr == 0)
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Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
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if (!MO.isJTI() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(Expr,
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MCConstantExpr::Create(MO.getOffset(), Ctx),
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Ctx);
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return MCOperand::CreateExpr(Expr);
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}
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static void lower_subreg32(MCInst *MI, unsigned OpNo) {
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// Convert registers in the addr mode according to subreg32.
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unsigned Reg = MI->getOperand(OpNo).getReg();
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if (Reg != 0)
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MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
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}
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static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
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// Convert registers in the addr mode according to subreg64.
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for (unsigned i = 0; i != 4; ++i) {
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if (!MI->getOperand(OpNo+i).isReg()) continue;
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unsigned Reg = MI->getOperand(OpNo+i).getReg();
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if (Reg == 0) continue;
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MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
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}
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}
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/// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
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static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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lower_subreg32(&OutMI, 0);
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}
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/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
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static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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OutMI.addOperand(OutMI.getOperand(0));
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OutMI.addOperand(OutMI.getOperand(0));
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}
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void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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MI->dump();
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) continue;
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
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MO.getMBB()->getSymbol(), Ctx));
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = LowerSymbolOperand(MO,
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AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
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break;
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}
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OutMI.addOperand(MCOp);
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}
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// Handle a few special cases to eliminate operand modifiers.
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switch (OutMI.getOpcode()) {
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case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
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lower_lea64_32mem(&OutMI, 1);
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break;
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case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
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case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
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case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
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case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
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case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
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case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
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case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
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case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
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case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
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case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
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case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
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case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
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case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
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case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
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case X86::MMX_V_SETALLONES:
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LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
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case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
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case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
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case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
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case X86::MOV16r0:
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LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
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LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
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break;
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case X86::MOV64r0:
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LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
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LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
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break;
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// The assembler backend wants to see branches in their small form and relax
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// them to their large form. The JIT can only handle the large form because
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// it does not do relaxation. For now, translate the large form to the
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// small one here.
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case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
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case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
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case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
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case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
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case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
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case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
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case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
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case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
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case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
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case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
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case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
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case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
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case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
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case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
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case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
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case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
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case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
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}
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}
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void X86AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
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raw_ostream &O) {
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// Only the target-dependent form of DBG_VALUE should get here.
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// Referencing the offset and metadata as NOps-2 and NOps-1 is
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// probably portable to other targets; frame pointer location is not.
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unsigned NOps = MI->getNumOperands();
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assert(NOps==7);
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O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
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// cast away const; DIetc do not take const operands for some reason.
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DIVariable V((MDNode*)(MI->getOperand(NOps-1).getMetadata()));
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O << V.getName();
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O << " <- ";
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// Frame address. Currently handles register +- offset only.
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assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm());
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O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O);
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O << ']';
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O << "+";
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printOperand(MI, NOps-2, O);
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}
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void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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X86MCInstLower MCInstLowering(OutContext, Mang, *this);
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switch (MI->getOpcode()) {
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case TargetOpcode::DBG_VALUE:
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if (isVerbose() && OutStreamer.hasRawTextSupport()) {
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std::string TmpStr;
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raw_string_ostream OS(TmpStr);
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PrintDebugValueComment(MI, OS);
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OutStreamer.EmitRawText(StringRef(OS.str()));
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}
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return;
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case X86::MOVPC32r: {
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MCInst TmpInst;
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// This is a pseudo op for a two instruction sequence with a label, which
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// looks like:
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// call "L1$pb"
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// "L1$pb":
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// popl %esi
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// Emit the call.
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MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
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TmpInst.setOpcode(X86::CALLpcrel32);
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// FIXME: We would like an efficient form for this, so we don't have to do a
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// lot of extra uniquing.
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TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
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OutContext)));
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OutStreamer.EmitInstruction(TmpInst);
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// Emit the label.
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OutStreamer.EmitLabel(PICBase);
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// popl $reg
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TmpInst.setOpcode(X86::POP32r);
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TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
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OutStreamer.EmitInstruction(TmpInst);
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return;
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}
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|
|
case X86::ADD32ri: {
|
|
// Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
|
|
if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
|
|
break;
|
|
|
|
// Okay, we have something like:
|
|
// EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
|
|
|
|
// For this, we want to print something like:
|
|
// MYGLOBAL + (. - PICBASE)
|
|
// However, we can't generate a ".", so just emit a new label here and refer
|
|
// to it.
|
|
MCSymbol *DotSym = OutContext.CreateTempSymbol();
|
|
OutStreamer.EmitLabel(DotSym);
|
|
|
|
// Now that we have emitted the label, lower the complex operand expression.
|
|
MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
|
|
|
|
const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
|
|
const MCExpr *PICBase =
|
|
MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
|
|
DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
|
|
|
|
DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
|
|
DotExpr, OutContext);
|
|
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(X86::ADD32ri);
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
return;
|
|
}
|
|
}
|
|
|
|
MCInst TmpInst;
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
|