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https://github.com/c64scene-ar/llvm-6502.git
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82a87a0172
with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
360 lines
12 KiB
C++
360 lines
12 KiB
C++
//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "InstrInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "Record.h"
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#include <algorithm>
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using namespace llvm;
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// runEnums - Print out enum values for all of the instructions.
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void InstrInfoEmitter::runEnums(std::ostream &OS) {
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EmitSourceFileHeader("Target Instruction Enum Values", OS);
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OS << "namespace llvm {\n\n";
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CodeGenTarget Target;
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// We must emit the PHI opcode first...
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std::string Namespace;
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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if (II->second.Namespace != "TargetInstrInfo") {
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Namespace = II->second.Namespace;
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break;
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}
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}
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if (Namespace.empty()) {
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cerr << "No instructions defined!\n";
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exit(1);
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}
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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OS << "namespace " << Namespace << " {\n";
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OS << " enum {\n";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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OS << " " << NumberedInstructions[i]->TheDef->getName()
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<< "\t= " << i << ",\n";
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}
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OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
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OS << " };\n}\n";
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OS << "} // End llvm namespace \n";
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}
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void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
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unsigned Num, std::ostream &OS) const {
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OS << "static const unsigned ImplicitList" << Num << "[] = { ";
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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OS << getQualifiedName(Uses[i]) << ", ";
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OS << "0 };\n";
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}
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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std::vector<CodeGenInstruction::OperandInfo> OperandList;
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandList.push_back(Inst.OperandList[i]);
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} else {
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for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
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OperandList.push_back(Inst.OperandList[i]);
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Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
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OperandList.back().Rec = OpR;
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}
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}
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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else
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Res += "0, ";
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// Fill in applicable flags.
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Res += "0";
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// Ptr value whose register class is resolved via callback.
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if (OpR->getName() == "ptr_rc")
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Res += "|M_LOOK_UP_PTR_REG_CLASS";
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOperand.
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if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
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Res += "|M_PREDICATE_OPERAND";
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// Fill in constraint info.
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Res += ", " + Inst.OperandList[i].Constraints[j];
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Result.push_back(Res);
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}
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}
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return Result;
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}
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// run - Emit the main instruction description records for the target...
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void InstrInfoEmitter::run(std::ostream &OS) {
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GatherItinClasses();
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EmitSourceFileHeader("Target Instruction Descriptors", OS);
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OS << "namespace llvm {\n\n";
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CodeGenTarget Target;
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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unsigned ListNumber = 0;
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// Emit all of the instruction's implicit uses and defs.
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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Record *Inst = II->second.TheDef;
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std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
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if (!Uses.empty()) {
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unsigned &IL = EmittedLists[Uses];
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if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
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}
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std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
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if (!Defs.empty()) {
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unsigned &IL = EmittedLists[Defs];
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if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
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}
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}
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std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
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unsigned OperandListNum = 0;
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OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
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// Emit all of the operand info records.
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OS << "\n";
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
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unsigned &N = OperandInfosEmitted[OperandInfo];
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if (N == 0) {
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N = ++OperandListNum;
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OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
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for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
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OS << "{ " << OperandInfo[i] << " }, ";
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OS << "};\n";
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}
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}
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// Emit all of the TargetInstrDescriptor records in their ENUM ordering.
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//
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OS << "\nstatic const TargetInstrDescriptor " << TargetName
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<< "Insts[] = {\n";
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
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emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
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OperandInfosEmitted, OS);
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OS << "};\n";
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OS << "} // End llvm namespace \n";
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}
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void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EmittedLists,
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std::map<std::vector<std::string>, unsigned> &OpInfo,
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std::ostream &OS) {
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int MinOperands;
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if (!Inst.OperandList.empty())
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// Each logical operand can be multiple MI operands.
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MinOperands = Inst.OperandList.back().MIOperandNo +
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Inst.OperandList.back().MINumOperands;
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else
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MinOperands = 0;
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OS << " { ";
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OS << Num << ",\t" << MinOperands << ",\t\"";
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if (Inst.Name.empty())
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OS << Inst.TheDef->getName();
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else
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OS << Inst.Name;
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unsigned ItinClass = !IsItineraries ? 0 :
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ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
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OS << "\",\t" << ItinClass << ", 0";
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// Try to determine (from the pattern), if the instruction is a store.
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bool isStore = false;
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if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
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ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
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if (LI && LI->getSize() > 0) {
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DagInit *Dag = (DagInit *)LI->getElement(0);
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DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
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if (OpDef) {
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Record *Operator = OpDef->getDef();
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if (Operator->isSubClassOf("SDNode")) {
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const std::string Opcode = Operator->getValueAsString("Opcode");
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if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
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isStore = true;
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}
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}
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}
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}
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// Emit all of the target indepedent flags...
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if (Inst.isReturn) OS << "|M_RET_FLAG";
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if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
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if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
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if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
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if (Inst.isCall) OS << "|M_CALL_FLAG";
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if (Inst.isLoad) OS << "|M_LOAD_FLAG";
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if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
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if (Inst.isPredicable) OS << "|M_PREDICABLE";
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if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
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if (Inst.isCommutable) OS << "|M_COMMUTABLE";
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if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
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if (Inst.clobbersPred) OS << "|M_CLOBBERS_PRED";
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if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
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if (Inst.usesCustomDAGSchedInserter)
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OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
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if (Inst.hasVariableNumberOfOperands)
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OS << "|M_VARIABLE_OPS";
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OS << ", 0";
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// Emit all of the target-specific flags...
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ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
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ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
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if (LI->getSize() != Shift->getSize())
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throw "Lengths of " + InstrInfo->getName() +
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":(TargetInfoFields, TargetInfoPositions) must be equal!";
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for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
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emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
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dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
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OS << ", ";
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// Emit the implicit uses and defs lists...
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std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
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if (UseList.empty())
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OS << "NULL, ";
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else
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OS << "ImplicitList" << EmittedLists[UseList] << ", ";
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std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
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if (DefList.empty())
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OS << "NULL, ";
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else
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OS << "ImplicitList" << EmittedLists[DefList] << ", ";
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// Emit the operand info.
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std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
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if (OperandInfo.empty())
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OS << "0";
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else
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OS << "OperandInfo" << OpInfo[OperandInfo];
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OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
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}
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struct LessRecord {
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bool operator()(const Record *Rec1, const Record *Rec2) const {
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return Rec1->getName() < Rec2->getName();
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}
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};
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void InstrInfoEmitter::GatherItinClasses() {
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std::vector<Record*> DefList =
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Records.getAllDerivedDefinitions("InstrItinClass");
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IsItineraries = !DefList.empty();
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if (!IsItineraries) return;
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std::sort(DefList.begin(), DefList.end(), LessRecord());
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for (unsigned i = 0, N = DefList.size(); i < N; i++) {
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Record *Def = DefList[i];
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ItinClassMap[Def->getName()] = i;
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}
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}
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unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
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return ItinClassMap[ItinName];
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}
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void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
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IntInit *ShiftInt, std::ostream &OS) {
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if (Val == 0 || ShiftInt == 0)
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throw std::string("Illegal value or shift amount in TargetInfo*!");
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RecordVal *RV = R->getValue(Val->getValue());
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int Shift = ShiftInt->getValue();
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if (RV == 0 || RV->getValue() == 0) {
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// This isn't an error if this is a builtin instruction.
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if (R->getName() != "PHI" &&
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R->getName() != "INLINEASM" &&
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R->getName() != "LABEL")
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throw R->getName() + " doesn't have a field named '" +
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Val->getValue() + "'!";
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return;
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}
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Init *Value = RV->getValue();
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if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
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if (BI->getValue()) OS << "|(1<<" << Shift << ")";
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return;
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} else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
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// Convert the Bits to an integer to print...
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Init *I = BI->convertInitializerTo(new IntRecTy());
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if (I)
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if (IntInit *II = dynamic_cast<IntInit*>(I)) {
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if (II->getValue()) {
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if (Shift)
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OS << "|(" << II->getValue() << "<<" << Shift << ")";
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else
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OS << "|" << II->getValue();
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}
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return;
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}
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} else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
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if (II->getValue()) {
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if (Shift)
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OS << "|(" << II->getValue() << "<<" << Shift << ")";
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else
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OS << II->getValue();
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}
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return;
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}
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cerr << "Unhandled initializer: " << *Val << "\n";
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throw "In record '" + R->getName() + "' for TSFlag emission.";
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}
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