Tom Stellard d40758b24e DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes ... DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two mistakes: 1. It was checking the legality of scalar INT_TO_FP nodes and then generating vector nodes. 2. It was passing the result value type to TargetLoweringInfo::getOperationAction() when it should have been passing the value type of the first operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171420 91177308-0d34-0410-b5e6-96231b3b80d8		2013-01-02 22:13:01 +00:00
..
ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon	In hexagon convertToHardwareLoop, don't deref end() iterator	2012-12-07 21:03:15 +00:00
MBlaze
Mips	Add test case for r170674	2012-12-21 00:55:10 +00:00
MSP430	Add support for varargs functions for msp430.	2012-11-21 17:28:27 +00:00
NVPTX	[NVPTX] Fix crash with unnamed struct arguments	2012-12-05 20:50:28 +00:00
PowerPC	Support ppcf128 in SelectionDAG::getConstantFP	2012-12-30 19:03:32 +00:00
R600	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC
Thumb	Use the 'count' attribute to calculate the upper bound of an array.	2012-12-04 21:34:03 +00:00
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
XCore	Fix handling of aliases to functions.	2012-11-16 21:12:38 +00:00