mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-07 05:55:44 +00:00
477fc628b3
Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.6 KiB
LLVM
121 lines
3.6 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @add8xi8(<8 x i8> %A, <8 x i8> %B) {
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;CHECK: add {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
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%tmp3 = add <8 x i8> %A, %B;
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @add16xi8(<16 x i8> %A, <16 x i8> %B) {
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;CHECK: add {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
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%tmp3 = add <16 x i8> %A, %B;
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @add4xi16(<4 x i16> %A, <4 x i16> %B) {
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;CHECK: add {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
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%tmp3 = add <4 x i16> %A, %B;
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ret <4 x i16> %tmp3
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}
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define <8 x i16> @add8xi16(<8 x i16> %A, <8 x i16> %B) {
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;CHECK: add {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
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%tmp3 = add <8 x i16> %A, %B;
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ret <8 x i16> %tmp3
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}
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define <2 x i32> @add2xi32(<2 x i32> %A, <2 x i32> %B) {
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;CHECK: add {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
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%tmp3 = add <2 x i32> %A, %B;
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @add4x32(<4 x i32> %A, <4 x i32> %B) {
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;CHECK: add {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
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%tmp3 = add <4 x i32> %A, %B;
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @add2xi64(<2 x i64> %A, <2 x i64> %B) {
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;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
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%tmp3 = add <2 x i64> %A, %B;
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ret <2 x i64> %tmp3
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}
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define <2 x float> @add2xfloat(<2 x float> %A, <2 x float> %B) {
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;CHECK: fadd {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
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%tmp3 = fadd <2 x float> %A, %B;
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ret <2 x float> %tmp3
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}
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define <4 x float> @add4xfloat(<4 x float> %A, <4 x float> %B) {
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;CHECK: fadd {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
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%tmp3 = fadd <4 x float> %A, %B;
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ret <4 x float> %tmp3
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}
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define <2 x double> @add2xdouble(<2 x double> %A, <2 x double> %B) {
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;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
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%tmp3 = fadd <2 x double> %A, %B;
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ret <2 x double> %tmp3
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}
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define <8 x i8> @sub8xi8(<8 x i8> %A, <8 x i8> %B) {
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;CHECK: sub {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
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%tmp3 = sub <8 x i8> %A, %B;
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @sub16xi8(<16 x i8> %A, <16 x i8> %B) {
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;CHECK: sub {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
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%tmp3 = sub <16 x i8> %A, %B;
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @sub4xi16(<4 x i16> %A, <4 x i16> %B) {
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;CHECK: sub {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
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%tmp3 = sub <4 x i16> %A, %B;
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ret <4 x i16> %tmp3
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}
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define <8 x i16> @sub8xi16(<8 x i16> %A, <8 x i16> %B) {
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;CHECK: sub {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
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%tmp3 = sub <8 x i16> %A, %B;
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ret <8 x i16> %tmp3
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}
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define <2 x i32> @sub2xi32(<2 x i32> %A, <2 x i32> %B) {
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;CHECK: sub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
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%tmp3 = sub <2 x i32> %A, %B;
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @sub4x32(<4 x i32> %A, <4 x i32> %B) {
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;CHECK: sub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
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%tmp3 = sub <4 x i32> %A, %B;
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @sub2xi64(<2 x i64> %A, <2 x i64> %B) {
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;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
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%tmp3 = sub <2 x i64> %A, %B;
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ret <2 x i64> %tmp3
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}
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define <2 x float> @sub2xfloat(<2 x float> %A, <2 x float> %B) {
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;CHECK: fsub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
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%tmp3 = fsub <2 x float> %A, %B;
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ret <2 x float> %tmp3
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}
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define <4 x float> @sub4xfloat(<4 x float> %A, <4 x float> %B) {
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;CHECK: fsub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
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%tmp3 = fsub <4 x float> %A, %B;
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ret <4 x float> %tmp3
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}
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define <2 x double> @sub2xdouble(<2 x double> %A, <2 x double> %B) {
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;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
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%tmp3 = fsub <2 x double> %A, %B;
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ret <2 x double> %tmp3
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}
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