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8306968c147d5861d8a53fba86ac0fbf5c050b84
llvm-6502/test/CodeGen
T
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Chris Lattner 8306968c14 implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:51:22 +00:00
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Alpha
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ARM
Revert svn 107892 (with changes to work with trunk). It caused a crash if
2010-08-26 00:13:36 +00:00
Blackfin
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CBackend
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CellSPU
Fix SPU BE to use all the available return registers.
2010-08-24 11:50:48 +00:00
CPP
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Generic
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MBlaze
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Mips
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MSP430
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PIC16
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PowerPC
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SPARC
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SystemZ
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Thumb
Enable pre-RA virtual frame base register allocation. rdar://8277890
2010-08-26 00:58:06 +00:00
Thumb2
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
2010-08-25 16:58:05 +00:00
X86
implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
2010-08-26 05:51:22 +00:00
XCore
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