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https://github.com/c64scene-ar/llvm-6502.git
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830f3f205d
case, instcombine can't zap the invoke for fear of changing the CFG. However, we have to do something to prevent the next iteration of instcombine from inserting another store -> undef before the invoke thereby getting into infinite iteration between dead store elim and store insertion. Just zap the callee to null, which will prevent the next iteration from doing anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94985 91177308-0d34-0410-b5e6-96231b3b80d8
229 lines
7.4 KiB
LLVM
229 lines
7.4 KiB
LLVM
; RUN: opt < %s -instcombine -S
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128:n8:16:32"
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target triple = "i386-apple-darwin10.0"
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define i32 @test0(i8 %tmp2) ssp {
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entry:
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%tmp3 = zext i8 %tmp2 to i32
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%tmp8 = lshr i32 %tmp3, 6
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%tmp9 = lshr i32 %tmp3, 7
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%tmp10 = xor i32 %tmp9, 67108858
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%tmp11 = xor i32 %tmp10, %tmp8
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%tmp12 = xor i32 %tmp11, 0
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ret i32 %tmp12
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}
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; PR4905
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define <2 x i64> @test1(<2 x i64> %x, <2 x i64> %y) nounwind {
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entry:
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%conv.i94 = bitcast <2 x i64> %y to <4 x i32> ; <<4 x i32>> [#uses=1]
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%sub.i97 = sub <4 x i32> %conv.i94, undef ; <<4 x i32>> [#uses=1]
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%conv3.i98 = bitcast <4 x i32> %sub.i97 to <2 x i64> ; <<2 x i64>> [#uses=2]
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%conv2.i86 = bitcast <2 x i64> %conv3.i98 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%cmp.i87 = icmp sgt <4 x i32> undef, %conv2.i86 ; <<4 x i1>> [#uses=1]
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%sext.i88 = sext <4 x i1> %cmp.i87 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%conv3.i89 = bitcast <4 x i32> %sext.i88 to <2 x i64> ; <<2 x i64>> [#uses=1]
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%and.i = and <2 x i64> %conv3.i89, %conv3.i98 ; <<2 x i64>> [#uses=1]
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%or.i = or <2 x i64> zeroinitializer, %and.i ; <<2 x i64>> [#uses=1]
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%conv2.i43 = bitcast <2 x i64> %or.i to <4 x i32> ; <<4 x i32>> [#uses=1]
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%sub.i = sub <4 x i32> zeroinitializer, %conv2.i43 ; <<4 x i32>> [#uses=1]
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%conv3.i44 = bitcast <4 x i32> %sub.i to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %conv3.i44
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}
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; PR4908
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define void @test2(<1 x i16>* nocapture %b, i32* nocapture %c) nounwind ssp {
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entry:
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%arrayidx = getelementptr inbounds <1 x i16>* %b, i64 undef ; <<1 x i16>*>
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%tmp2 = load <1 x i16>* %arrayidx ; <<1 x i16>> [#uses=1]
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%tmp6 = bitcast <1 x i16> %tmp2 to i16 ; <i16> [#uses=1]
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%tmp7 = zext i16 %tmp6 to i32 ; <i32> [#uses=1]
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%ins = or i32 0, %tmp7 ; <i32> [#uses=1]
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%arrayidx20 = getelementptr inbounds i32* %c, i64 undef ; <i32*> [#uses=1]
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store i32 %ins, i32* %arrayidx20
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ret void
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}
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; PR5262
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@tmp2 = global i64 0 ; <i64*> [#uses=1]
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declare void @use(i64) nounwind
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define void @foo(i1) nounwind align 2 {
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; <label>:1
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br i1 %0, label %2, label %3
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; <label>:2 ; preds = %1
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br label %3
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; <label>:3 ; preds = %2, %1
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%4 = phi i8 [ 1, %2 ], [ 0, %1 ] ; <i8> [#uses=1]
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%5 = icmp eq i8 %4, 0 ; <i1> [#uses=1]
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%6 = load i64* @tmp2, align 8 ; <i64> [#uses=1]
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%7 = select i1 %5, i64 0, i64 %6 ; <i64> [#uses=1]
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br label %8
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; <label>:8 ; preds = %3
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call void @use(i64 %7)
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ret void
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}
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%t0 = type { i32, i32 }
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%t1 = type { i32, i32, i32, i32, i32* }
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declare %t0* @bar2(i64)
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define void @bar3(i1, i1) nounwind align 2 {
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; <label>:2
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br i1 %1, label %10, label %3
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; <label>:3 ; preds = %2
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%4 = getelementptr inbounds %t0* null, i64 0, i32 1 ; <i32*> [#uses=0]
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%5 = getelementptr inbounds %t1* null, i64 0, i32 4 ; <i32**> [#uses=1]
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%6 = load i32** %5, align 8 ; <i32*> [#uses=1]
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%7 = icmp ne i32* %6, null ; <i1> [#uses=1]
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%8 = zext i1 %7 to i32 ; <i32> [#uses=1]
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%9 = add i32 %8, 0 ; <i32> [#uses=1]
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br label %10
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; <label>:10 ; preds = %3, %2
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%11 = phi i32 [ %9, %3 ], [ 0, %2 ] ; <i32> [#uses=1]
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br i1 %1, label %12, label %13
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; <label>:12 ; preds = %10
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br label %13
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; <label>:13 ; preds = %12, %10
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%14 = zext i32 %11 to i64 ; <i64> [#uses=1]
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%15 = tail call %t0* @bar2(i64 %14) nounwind ; <%0*> [#uses=0]
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ret void
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}
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; PR5262
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; Make sure the PHI node gets put in a place where all of its operands dominate
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; it.
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define i64 @test4(i1 %c, i64* %P) nounwind align 2 {
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BB0:
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br i1 %c, label %BB1, label %BB2
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BB1:
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br label %BB2
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BB2:
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%v5_ = phi i1 [ true, %BB0], [false, %BB1]
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%v6 = load i64* %P
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br label %l8
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l8:
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br label %l10
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l10:
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%v11 = select i1 %v5_, i64 0, i64 %v6
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ret i64 %v11
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}
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; PR5471
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define arm_apcscc i32 @test5a() {
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ret i32 0
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}
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define arm_apcscc void @test5() {
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store i1 true, i1* undef
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%1 = invoke i32 @test5a() to label %exit unwind label %exit
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exit:
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ret void
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}
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; PR5673
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@test6g = external global i32*
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define arm_aapcs_vfpcc i32 @test6(i32 %argc, i8** %argv) nounwind {
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entry:
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store i32* getelementptr (i32* bitcast (i32 (i32, i8**)* @test6 to i32*), i32 -2048), i32** @test6g, align 4
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unreachable
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}
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; PR5827
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%class.RuleBasedBreakIterator = type { i64 ()* }
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%class.UStack = type { i8** }
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define i32 @_ZN22RuleBasedBreakIterator15checkDictionaryEi(%class.RuleBasedBreakIterator* %this, i32 %x) align 2 {
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entry:
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%breaks = alloca %class.UStack, align 4 ; <%class.UStack*> [#uses=3]
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call void @_ZN6UStackC1Ei(%class.UStack* %breaks, i32 0)
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%tobool = icmp ne i32 %x, 0 ; <i1> [#uses=1]
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br i1 %tobool, label %cond.end, label %cond.false
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terminate.handler: ; preds = %ehcleanup
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%exc = call i8* @llvm.eh.exception() ; <i8*> [#uses=1]
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%0 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 1) ; <i32> [#uses=0]
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call void @_ZSt9terminatev() noreturn nounwind
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unreachable
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ehcleanup: ; preds = %cond.false
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%exc1 = call i8* @llvm.eh.exception() ; <i8*> [#uses=2]
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%1 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc1, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) ; <i32> [#uses=0]
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invoke void @_ZN6UStackD1Ev(%class.UStack* %breaks)
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to label %cont unwind label %terminate.handler
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cont: ; preds = %ehcleanup
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call void @_Unwind_Resume_or_Rethrow(i8* %exc1)
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unreachable
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cond.false: ; preds = %entry
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%tmp4 = getelementptr inbounds %class.RuleBasedBreakIterator* %this, i32 0, i32 0 ; <i64 ()**> [#uses=1]
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%tmp5 = load i64 ()** %tmp4 ; <i64 ()*> [#uses=1]
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%call = invoke i64 %tmp5()
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to label %cond.end unwind label %ehcleanup ; <i64> [#uses=1]
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cond.end: ; preds = %cond.false, %entry
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%cond = phi i64 [ 0, %entry ], [ %call, %cond.false ] ; <i64> [#uses=1]
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%conv = trunc i64 %cond to i32 ; <i32> [#uses=1]
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call void @_ZN6UStackD1Ev(%class.UStack* %breaks)
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ret i32 %conv
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}
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declare void @_ZN6UStackC1Ei(%class.UStack*, i32)
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declare void @_ZN6UStackD1Ev(%class.UStack*)
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declare i32 @__gxx_personality_v0(...)
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declare i8* @llvm.eh.exception() nounwind readonly
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declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind
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declare void @_ZSt9terminatev()
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declare void @_Unwind_Resume_or_Rethrow(i8*)
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; rdar://7590304
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define i8* @test10(i8* %self, i8* %tmp3) {
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entry:
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store i1 true, i1* undef
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store i1 true, i1* undef
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invoke arm_apcscc void @test10a()
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to label %invoke.cont unwind label %try.handler ; <i8*> [#uses=0]
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invoke.cont: ; preds = %entry
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unreachable
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try.handler: ; preds = %entry
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ret i8* %self
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}
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define void @test10a() {
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ret void
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}
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