mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
db1c494276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211800 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.3 KiB
C++
71 lines
2.3 KiB
C++
//===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file declares the X86 specific subclass of TargetMachine.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef X86TARGETMACHINE_H
|
|
#define X86TARGETMACHINE_H
|
|
#include "X86InstrInfo.h"
|
|
#include "X86Subtarget.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
namespace llvm {
|
|
|
|
class StringRef;
|
|
|
|
class X86TargetMachine final : public LLVMTargetMachine {
|
|
virtual void anchor();
|
|
X86Subtarget Subtarget;
|
|
|
|
public:
|
|
X86TargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL);
|
|
|
|
const DataLayout *getDataLayout() const override {
|
|
return getSubtargetImpl()->getDataLayout();
|
|
}
|
|
const X86InstrInfo *getInstrInfo() const override {
|
|
return getSubtargetImpl()->getInstrInfo();
|
|
}
|
|
const TargetFrameLowering *getFrameLowering() const override {
|
|
return getSubtargetImpl()->getFrameLowering();
|
|
}
|
|
X86JITInfo *getJITInfo() override { return Subtarget.getJITInfo(); }
|
|
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
|
|
const X86TargetLowering *getTargetLowering() const override {
|
|
return getSubtargetImpl()->getTargetLowering();
|
|
}
|
|
const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
|
|
return getSubtargetImpl()->getSelectionDAGInfo();
|
|
}
|
|
const X86RegisterInfo *getRegisterInfo() const override {
|
|
return &getInstrInfo()->getRegisterInfo();
|
|
}
|
|
const InstrItineraryData *getInstrItineraryData() const override {
|
|
return &getSubtargetImpl()->getInstrItineraryData();
|
|
}
|
|
|
|
/// \brief Register X86 analysis passes with a pass manager.
|
|
void addAnalysisPasses(PassManagerBase &PM) override;
|
|
|
|
// Set up the pass pipeline.
|
|
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
|
|
|
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|