Jack Carter d3107fbc54 Fix the invalid opcode for Mips branch instructions in the assembler ... For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-22 00:29:10 +00:00
..
CMakeLists.txt	Forgot to add new file to CMakeLists	2013-01-30 02:32:36 +00:00
LLVMBuild.txt
Makefile
MipsAsmBackend.cpp
MipsBaseInfo.h
MipsDirectObjLower.cpp
MipsDirectObjLower.h
MipsELFObjectWriter.cpp
MipsELFStreamer.cpp	ELF symbol table field st_other support,	2013-02-19 22:29:00 +00:00
MipsELFStreamer.h	ELF symbol table field st_other support,	2013-02-19 22:04:37 +00:00
MipsFixupKinds.h
MipsMCAsmInfo.cpp
MipsMCAsmInfo.h
MipsMCCodeEmitter.cpp	Fix the invalid opcode for Mips branch instructions in the assembler	2013-03-22 00:29:10 +00:00
MipsMCTargetDesc.cpp
MipsMCTargetDesc.h
MipsReginfo.cpp
MipsReginfo.h