Hal Finkel 838a7fb1a3 RegScavenger should not exclude undef uses ... When computing currently-live registers, the register scavenger excludes undef uses. As a result, undef uses are ignored when computing the restore points of registers spilled into the emergency slots. While the register scavenger normally excludes from consideration, when scavenging, registers used by the current instruction, we need to not exclude undef uses. Otherwise, we might end up requiring more emergency spill slots than we have (in the case where the undef use *is* the currently-spilled register). Another bug found by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186067 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-11 05:55:57 +00:00
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AArch64	AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all	2013-07-09 18:16:56 +00:00
ARM	Add a comment to this change, requested by Eric Christopher.	2013-07-08 19:52:51 +00:00
CPP
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon
Inputs
MBlaze
Mips	[mips] Fix test case to check that mips64 instructions are generated.	2013-07-01 20:18:58 +00:00
MSP430	Really fix the test. Sorry for the breakage...	2013-07-01 19:51:36 +00:00
NVPTX	[NVPTX] Add support for module-scope inline asm	2013-07-01 13:00:14 +00:00
PowerPC	RegScavenger should not exclude undef uses	2013-07-11 05:55:57 +00:00
R600	R600/SI: Initial local memory support	2013-07-10 16:37:07 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Use MVC for simple load/store pairs	2013-07-09 09:46:39 +00:00
Thumb
Thumb2	ARM: Fix incorrect pack pattern for thumb2	2013-07-09 22:59:22 +00:00
X86	Move r186044 tests into CodeGen/X86	2013-07-11 01:55:55 +00:00
XCore	[XCore] Add ISel pattern for LDWCP	2013-07-03 07:48:50 +00:00