llvm-6502/2008-02-04-ExtractSubvector.ll at 838dbd92d8a4b979ec1d266884ebad55f6ae6998 - llvm-6502 - Applefritter: Git

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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-01 15:11:24 +00:00

Dan Gohman ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate

integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8

2009-06-04 22:49:04 +00:00

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 ; RUN: llvm-as < %s | llc
 define i32 @main() nounwind  {
 entry:
 	br label %bb15
 bb15:		; preds = %bb15, %entry
 	%tmp21 = fadd <8 x double> zeroinitializer, zeroinitializer		; <<8 x double>> [#uses=1]
 	br i1 false, label %bb30, label %bb15
 bb30:		; preds = %bb15
 	store <8 x double> %tmp21, <8 x double>* null, align 64
 	ret i32 0
 }