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a6afad8b33
There are two add-immediate instructions in Thumb1: tADDi8 and tADDi3. Only the latter supports using different source and destination registers, so whenever we materialize a new base register (at a certain offset) we'd do so by moving the base register value to the new register and then adding in place. This patch changes the code to use a single tADDi3 if the offset is small enough to fit in 3 bits. Differential Revision: http://reviews.llvm.org/D5006 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216193 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1016 B
LLVM
30 lines
1016 B
LLVM
; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-none--eabi"
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@a = external global i32*
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@b = external global i32*
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; Function Attrs: nounwind
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define void @foo() #0 {
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entry:
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; CHECK-LABEL: foo:
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; CHECK: ldr r[[SB:[0-9]]], .LCPI
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; CHECK: ldr r[[LB:[0-9]]], .LCPI
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; CHECK: adds r[[NLB:[0-9]]], r[[LB]], #4
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; CHECK-NEXT: ldm r[[NLB]],
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; CHECK: adds r[[NSB:[0-9]]], r[[SB]], #4
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; CHECK-NEXT: stm r[[NSB]]
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%0 = load i32** @a, align 4
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%arrayidx = getelementptr inbounds i32* %0, i32 1
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%1 = bitcast i32* %arrayidx to i8*
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%2 = load i32** @b, align 4
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%arrayidx1 = getelementptr inbounds i32* %2, i32 1
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%3 = bitcast i32* %arrayidx1 to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %3, i32 24, i32 4, i1 false)
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1
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