mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
4.4 KiB
LLVM
119 lines
4.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32:
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; SI-NOT: and
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; SI: v_sub_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}|
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define void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) {
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fadd = fadd float %y, %fsub
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store float %fadd, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fmul_f32:
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; SI-NOT: and
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; SI: v_mul_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}|
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; SI-NOT: and
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define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fmul = fmul float %y, %fsub
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store float %fmul, float addrspace(1)* %out, align 4
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ret void
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}
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; DAGCombiner will transform:
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; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; FUNC-LABEL: {{^}}fneg_fabs_free_f32:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f32:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_f32:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_fneg_fabs_f32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%val = load float, float addrspace(1)* %in, align 4
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%fabs = call float @llvm.fabs.f32(float %val)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v2f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: -PV
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: -PV
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; FIXME: SGPR should be used directly for first src operand.
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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%fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
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store <2 x float> %fsub, <2 x float> addrspace(1)* %out
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ret void
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}
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; FIXME: SGPR should be used directly for first src operand.
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; FUNC-LABEL: {{^}}fneg_fabs_v4f32:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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%fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
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store <4 x float> %fsub, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @fabs(float) readnone
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declare float @llvm.fabs.f32(float) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
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