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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
3.0 KiB
LLVM
75 lines
3.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare float @llvm.sqrt.f32(float) nounwind readnone
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declare double @llvm.sqrt.f64(double) nounwind readnone
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; SI-LABEL: {{^}}rsq_f32:
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; SI: v_rsq_f32_e32
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; SI: s_endpgm
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define void @rsq_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%val = load float, float addrspace(1)* %in, align 4
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%sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
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%div = fdiv float 1.0, %sqrt
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store float %div, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}rsq_f64:
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; SI-UNSAFE: v_rsq_f64_e32
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; SI-SAFE: v_sqrt_f64_e32
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; SI: s_endpgm
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define void @rsq_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) nounwind {
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%val = load double, double addrspace(1)* %in, align 4
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%sqrt = call double @llvm.sqrt.f64(double %val) nounwind readnone
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%div = fdiv double 1.0, %sqrt
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store double %div, double addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}rsq_f32_sgpr:
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; SI: s_endpgm
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define void @rsq_f32_sgpr(float addrspace(1)* noalias %out, float %val) nounwind {
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%sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
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%div = fdiv float 1.0, %sqrt
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store float %div, float addrspace(1)* %out, align 4
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ret void
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}
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; Recognize that this is rsqrt(a) * rcp(b) * c,
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; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
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; SI-LABEL: @rsqrt_fmul
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; SI-UNSAFE-DAG: v_rsq_f32_e32 [[RSQA:v[0-9]+]], [[A]]
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; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCPB:v[0-9]+]], [[B]]
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; SI-UNSAFE-DAG: v_mul_f32_e32 [[TMP:v[0-9]+]], [[RCPB]], [[RSQA]]
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; SI-UNSAFE: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
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; SI-UNSAFE: buffer_store_dword [[RESULT]]
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; SI-SAFE-NOT: v_rsq_f32
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; SI: s_endpgm
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define void @rsqrt_fmul(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
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%a = load float, float addrspace(1)* %gep.0
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%b = load float, float addrspace(1)* %gep.1
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%c = load float, float addrspace(1)* %gep.2
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%x = call float @llvm.sqrt.f32(float %a)
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%y = fmul float %x, %b
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%z = fdiv float %c, %y
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store float %z, float addrspace(1)* %out.gep
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ret void
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}
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