mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
239 lines
7.0 KiB
LLVM
239 lines
7.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}ngroups_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[0].X
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; GCN: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @ngroups_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ngroups_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[0].Y
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @ngroups_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ngroups_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[0].Z
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @ngroups_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[0].W
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @global_size_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[1].X
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @global_size_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[1].Y
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @global_size_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[1].Z
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @local_size_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[1].W
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @local_size_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[2].X
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @local_size_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}get_work_dim:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], KC0[2].Z
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @get_work_dim (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.AMDGPU.read.workdim() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; The tgid values are stored in sgprs offset by the number of user sgprs.
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; Currently we always use exactly 2 user sgprs for the pointer to the
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; kernel arguments, but this may change in the future.
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; FUNC-LABEL: {{^}}tgid_x:
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], s4
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; GCN: buffer_store_dword [[VVAL]]
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define void @tgid_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tgid_y:
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], s5
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; GCN: buffer_store_dword [[VVAL]]
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define void @tgid_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tgid_z:
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6
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; GCN: buffer_store_dword [[VVAL]]
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define void @tgid_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tidig_x:
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; GCN: buffer_store_dword v0
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define void @tidig_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tidig_y:
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; GCN: buffer_store_dword v1
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define void @tidig_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tidig_z:
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; GCN: buffer_store_dword v2
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define void @tidig_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.ngroups.x() #0
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declare i32 @llvm.r600.read.ngroups.y() #0
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declare i32 @llvm.r600.read.ngroups.z() #0
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declare i32 @llvm.r600.read.global.size.x() #0
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declare i32 @llvm.r600.read.global.size.y() #0
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declare i32 @llvm.r600.read.global.size.z() #0
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declare i32 @llvm.r600.read.local.size.x() #0
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declare i32 @llvm.r600.read.local.size.y() #0
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declare i32 @llvm.r600.read.local.size.z() #0
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declare i32 @llvm.r600.read.tgid.x() #0
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declare i32 @llvm.r600.read.tgid.y() #0
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declare i32 @llvm.r600.read.tgid.z() #0
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declare i32 @llvm.r600.read.tidig.x() #0
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declare i32 @llvm.r600.read.tidig.y() #0
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declare i32 @llvm.r600.read.tidig.z() #0
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declare i32 @llvm.AMDGPU.read.workdim() #0
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attributes #0 = { readnone }
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