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https://github.com/c64scene-ar/llvm-6502.git
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843ee2e6a4
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
4.5 KiB
C++
144 lines
4.5 KiB
C++
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Transforms/IPO/PassManagerBuilder.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <iostream>
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using namespace llvm;
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static cl::
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opt<bool> DisableHardwareLoops(
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"disable-hexagon-hwloops", cl::Hidden,
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cl::desc("Disable Hardware Loops for Hexagon target"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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/// things to work on Win32 without this. Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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extern "C" void LLVMInitializeHexagonTarget() {
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// Register the target.
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RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
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}
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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///
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/// Hexagon_TODO: Do I need an aggregate alignment?
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///
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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TargetOptions Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
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Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget),
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InstrItins(&Subtarget.getInstrItineraryData()) {
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setMCUseCFI(false);
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}
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// addPassesForOptimizations - Allow the backend (target) to add Target
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// Independent Optimization passes to the Pass Manager.
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bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
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PM.add(createConstantPropagationPass());
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PM.add(createLoopSimplifyPass());
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PM.add(createDeadCodeEliminationPass());
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PM.add(createConstantPropagationPass());
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PM.add(createLoopUnrollPass());
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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return true;
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}
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
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class HexagonPassConfig : public TargetPassConfig {
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public:
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM,
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bool DisableVerifyFlag)
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: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreRegAlloc();
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virtual bool addPostRegAlloc();
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virtual bool addPreSched2();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM,
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bool DisableVerify) {
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return new HexagonPassConfig(this, PM, DisableVerify);
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}
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bool HexagonPassConfig::addInstSelector() {
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PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
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PM.add(createHexagonISelDag(getHexagonTargetMachine()));
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return false;
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}
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bool HexagonPassConfig::addPreRegAlloc() {
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if (!DisableHardwareLoops) {
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PM.add(createHexagonHardwareLoops());
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}
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return false;
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}
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bool HexagonPassConfig::addPostRegAlloc() {
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PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
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return true;
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}
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bool HexagonPassConfig::addPreSched2() {
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PM.add(createIfConverterPass());
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return true;
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}
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bool HexagonPassConfig::addPreEmitPass() {
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if (!DisableHardwareLoops) {
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PM.add(createHexagonFixupHwLoops());
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}
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// Expand Spill code for predicate registers.
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PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
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// Split up TFRcondsets into conditional transfers.
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PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
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return false;
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}
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