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https://github.com/c64scene-ar/llvm-6502.git
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922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
5.1 KiB
TableGen
111 lines
5.1 KiB
TableGen
//===- X86InstrCMovSetCC.td - Conditional Move and SetCC ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 conditional move and set on condition
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// instructions.
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//
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//===----------------------------------------------------------------------===//
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// SetCC instructions.
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multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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isCommutable = 1 in {
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def #NAME#16rr
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: I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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[(set GR16:$dst,
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(X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
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IIC_CMOV16_RR>,TB,OpSize;
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def #NAME#32rr
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: I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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!strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
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[(set GR32:$dst,
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(X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
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IIC_CMOV32_RR>, TB;
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def #NAME#64rr
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:RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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!strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
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[(set GR64:$dst,
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(X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
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IIC_CMOV32_RR>, TB;
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}
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" in {
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def #NAME#16rm
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: I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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CondNode, EFLAGS))], IIC_CMOV16_RM>,
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TB, OpSize;
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def #NAME#32rm
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: I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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!strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
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def #NAME#64rm
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:RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
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!strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
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[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
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CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
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} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
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} // end multiclass
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// Conditional Moves.
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defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>;
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defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
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defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>;
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defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
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defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>;
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defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
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defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
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defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>;
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defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>;
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defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>;
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defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>;
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defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>;
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defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>;
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defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>;
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defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>;
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defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>;
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// SetCC instructions.
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multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
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let Uses = [EFLAGS] in {
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def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
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!strconcat(Mnemonic, "\t$dst"),
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[(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
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IIC_SET_R>, TB;
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def m : I<opc, MRM0m, (outs), (ins i8mem:$dst),
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!strconcat(Mnemonic, "\t$dst"),
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[(store (X86setcc OpNode, EFLAGS), addr:$dst)],
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IIC_SET_M>, TB;
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} // Uses = [EFLAGS]
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}
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defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
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defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
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defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
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defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
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defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
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defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
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defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
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defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
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defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
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defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed
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defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set
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defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set
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defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than
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defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
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defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal
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defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than
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