mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a9f643432d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40672 91177308-0d34-0410-b5e6-96231b3b80d8
595 lines
20 KiB
C++
595 lines
20 KiB
C++
//===-- X86ATTAsmPrinter.cpp - Convert X86 LLVM code to AT&T assembly -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to AT&T format assembly
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// language. This printer is the output mechanism used by `llc'.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "X86ATTAsmPrinter.h"
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#include "X86.h"
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#include "X86COFF.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86TargetMachine.h"
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#include "X86TargetAsmInfo.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Module.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(EmittedInsts, "Number of machine instrs printed");
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static std::string computePICLabel(unsigned FnNum,
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const TargetAsmInfo *TAI,
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const X86Subtarget* Subtarget) {
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std::string label;
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if (Subtarget->isTargetDarwin())
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label = "\"L" + utostr_32(FnNum) + "$pb\"";
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else if (Subtarget->isTargetELF())
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label = ".Lllvm$" + utostr_32(FnNum) + "$piclabel";
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else
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assert(0 && "Don't know how to print PIC label!\n");
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return label;
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}
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/// getSectionForFunction - Return the section that we should emit the
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/// specified function body into.
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std::string X86ATTAsmPrinter::getSectionForFunction(const Function &F) const {
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switch (F.getLinkage()) {
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default: assert(0 && "Unknown linkage type!");
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case Function::InternalLinkage:
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case Function::DLLExportLinkage:
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case Function::ExternalLinkage:
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return TAI->getTextSection();
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case Function::WeakLinkage:
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case Function::LinkOnceLinkage:
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if (Subtarget->isTargetDarwin()) {
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return ".section __TEXT,__textcoal_nt,coalesced,pure_instructions";
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} else if (Subtarget->isTargetCygMing()) {
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return "\t.section\t.text$linkonce." + CurrentFnName + ",\"ax\"";
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} else {
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return "\t.section\t.llvm.linkonce.t." + CurrentFnName +
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",\"ax\",@progbits";
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}
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}
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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if (TAI->doesSupportDebugInformation()) {
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// Let PassManager know we need debug information and relay
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// the MachineModuleInfo address on to DwarfWriter.
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DW.SetModuleInfo(&getAnalysis<MachineModuleInfo>());
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}
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SetupMachineFunction(MF);
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O << "\n\n";
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// Print out constants referenced by the function
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EmitConstantPool(MF.getConstantPool());
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// Print out labels for the function.
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const Function *F = MF.getFunction();
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unsigned CC = F->getCallingConv();
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// Populate function information map. Actually, We don't want to populate
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// non-stdcall or non-fastcall functions' information right now.
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if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
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FunctionInfoMap[F] = *MF.getInfo<X86MachineFunctionInfo>();
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X86SharedAsmPrinter::decorateName(CurrentFnName, F);
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SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
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switch (F->getLinkage()) {
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default: assert(0 && "Unknown linkage type!");
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case Function::InternalLinkage: // Symbols default to internal.
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if (Subtarget->isTargetDarwin())
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// FIXME: This should be parameterized somewhere.
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EmitAlignment(4, F, 0, true, 0x90);
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else
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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break;
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case Function::DLLExportLinkage:
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DLLExportedFns.insert(Mang->makeNameProper(F->getName(), ""));
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//FALLS THROUGH
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case Function::ExternalLinkage:
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if (Subtarget->isTargetDarwin())
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// FIXME: This should be parameterized somewhere.
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EmitAlignment(4, F, 0, true, 0x90);
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else
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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O << "\t.globl\t" << CurrentFnName << "\n";
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break;
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case Function::LinkOnceLinkage:
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case Function::WeakLinkage:
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if (Subtarget->isTargetDarwin()) {
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// FIXME: This should be parameterized somewhere.
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EmitAlignment(4, F, 0, true, 0x90);
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << "\t.weak_definition\t" << CurrentFnName << "\n";
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} else if (Subtarget->isTargetCygMing()) {
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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O << "\t.globl " << CurrentFnName << "\n";
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O << "\t.linkonce discard\n";
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} else {
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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O << "\t.weak\t" << CurrentFnName << "\n";
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}
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break;
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}
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if (F->hasHiddenVisibility()) {
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if (const char *Directive = TAI->getHiddenDirective())
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O << Directive << CurrentFnName << "\n";
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} else if (F->hasProtectedVisibility()) {
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if (const char *Directive = TAI->getProtectedDirective())
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O << Directive << CurrentFnName << "\n";
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}
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if (Subtarget->isTargetELF())
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O << "\t.type\t" << CurrentFnName << ",@function\n";
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else if (Subtarget->isTargetCygMing()) {
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O << "\t.def\t " << CurrentFnName
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<< ";\t.scl\t" <<
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(F->getLinkage() == Function::InternalLinkage ? COFF::C_STAT : COFF::C_EXT)
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<< ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
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<< ";\t.endef\n";
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}
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O << CurrentFnName << ":\n";
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// Add some workaround for linkonce linkage on Cygwin\MinGW
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if (Subtarget->isTargetCygMing() &&
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(F->getLinkage() == Function::LinkOnceLinkage ||
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F->getLinkage() == Function::WeakLinkage))
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O << "Lllvm$workaround$fake$stub$" << CurrentFnName << ":\n";
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if (TAI->doesSupportDebugInformation()) {
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// Emit pre-function debug information.
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DW.BeginFunction(&MF);
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}
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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if (I->pred_begin() != I->pred_end()) {
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printBasicBlockLabel(I, true);
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O << '\n';
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}
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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printMachineInstruction(II);
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}
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}
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if (TAI->hasDotTypeDotSizeDirective())
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O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << "\n";
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if (TAI->doesSupportDebugInformation()) {
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// Emit post-function debug information.
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DW.EndFunction();
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}
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// Print out jump tables referenced by the function.
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EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
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// We didn't modify anything.
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return false;
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}
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static inline bool printGOT(TargetMachine &TM, const X86Subtarget* ST) {
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return ST->isPICStyleGOT() && TM.getRelocationModel() == Reloc::PIC_;
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}
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static inline bool printStub(TargetMachine &TM, const X86Subtarget* ST) {
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return ST->isPICStyleStub() && TM.getRelocationModel() != Reloc::Static;
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}
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void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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const char *Modifier, bool NotRIPRel) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_Register: {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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"Virtual registers should not make it this far!");
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O << '%';
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unsigned Reg = MO.getReg();
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if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
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MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ?
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MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
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((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
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Reg = getX86SubSuperRegister(Reg, VT);
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}
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for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
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O << (char)tolower(*Name);
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return;
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}
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case MachineOperand::MO_Immediate:
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if (!Modifier ||
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(strcmp(Modifier, "debug") && strcmp(Modifier, "mem")))
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O << '$';
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O << MO.getImmedValue();
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return;
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case MachineOperand::MO_MachineBasicBlock:
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printBasicBlockLabel(MO.getMachineBasicBlock());
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return;
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case MachineOperand::MO_JumpTableIndex: {
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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if (!isMemOp) O << '$';
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O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
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<< MO.getJumpTableIndex();
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if (Subtarget->isPICStyleStub())
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O << "-\"" << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
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<< "$pb\"";
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else if (Subtarget->isPICStyleGOT())
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O << "@GOTOFF";
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}
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if (isMemOp && Subtarget->isPICStyleRIPRel() && !NotRIPRel)
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O << "(%rip)";
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return;
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}
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case MachineOperand::MO_ConstantPoolIndex: {
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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if (!isMemOp) O << '$';
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O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
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<< MO.getConstantPoolIndex();
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if (Subtarget->isPICStyleStub())
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O << "-\"" << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
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<< "$pb\"";
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else if (Subtarget->isPICStyleGOT())
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O << "@GOTOFF";
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}
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int Offset = MO.getOffset();
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if (Offset > 0)
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O << "+" << Offset;
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else if (Offset < 0)
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O << Offset;
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if (isMemOp && Subtarget->isPICStyleRIPRel() && !NotRIPRel)
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O << "(%rip)";
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return;
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}
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case MachineOperand::MO_GlobalAddress: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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bool needCloseParen = false;
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GlobalValue *GV = MO.getGlobal();
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GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
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bool isThreadLocal = GVar && GVar->isThreadLocal();
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std::string Name = Mang->getValueName(GV);
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X86SharedAsmPrinter::decorateName(Name, GV);
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if (!isMemOp && !isCallOp)
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O << '$';
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else if (Name[0] == '$') {
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// The name begins with a dollar-sign. In order to avoid having it look
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// like an integer immediate to the assembler, enclose it in parens.
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O << '(';
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needCloseParen = true;
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}
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if (printStub(TM, Subtarget)) {
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// Link-once, declaration, or Weakly-linked global variables need
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// non-lazily-resolved stubs
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if (GV->isDeclaration() ||
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GV->hasWeakLinkage() ||
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GV->hasLinkOnceLinkage()) {
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// Dynamically-resolved functions need a stub for the function.
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if (isCallOp && isa<Function>(GV)) {
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FnStubs.insert(Name);
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O << TAI->getPrivateGlobalPrefix() << Name << "$stub";
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} else {
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GVStubs.insert(Name);
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O << TAI->getPrivateGlobalPrefix() << Name << "$non_lazy_ptr";
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}
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} else {
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if (GV->hasDLLImportLinkage())
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O << "__imp_";
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O << Name;
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}
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if (!isCallOp && TM.getRelocationModel() == Reloc::PIC_)
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O << "-\"" << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
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<< "$pb\"";
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} else {
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if (GV->hasDLLImportLinkage()) {
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O << "__imp_";
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}
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O << Name;
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if (isCallOp && isa<Function>(GV)) {
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if (printGOT(TM, Subtarget)) {
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// Assemble call via PLT for non-local symbols
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if (!(GV->hasHiddenVisibility() || GV->hasProtectedVisibility()) ||
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GV->isDeclaration())
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O << "@PLT";
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}
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if (Subtarget->isTargetCygMing() && GV->isDeclaration())
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// Save function name for later type emission
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FnStubs.insert(Name);
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}
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}
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if (GV->hasExternalWeakLinkage())
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ExtWeakSymbols.insert(GV);
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int Offset = MO.getOffset();
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if (Offset > 0)
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O << "+" << Offset;
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else if (Offset < 0)
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O << Offset;
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if (isThreadLocal) {
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if (TM.getRelocationModel() == Reloc::PIC_)
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O << "@TLSGD"; // general dynamic TLS model
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else
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if (GV->isDeclaration())
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O << "@INDNTPOFF"; // initial exec TLS model
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else
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O << "@NTPOFF"; // local exec TLS model
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} else if (isMemOp) {
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if (printGOT(TM, Subtarget)) {
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if (Subtarget->GVRequiresExtraLoad(GV, TM, false))
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O << "@GOT";
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else
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O << "@GOTOFF";
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} else if (Subtarget->isPICStyleRIPRel() && !NotRIPRel) {
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if ((GV->isDeclaration() ||
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GV->hasWeakLinkage() ||
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GV->hasLinkOnceLinkage()) &&
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TM.getRelocationModel() != Reloc::Static)
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O << "@GOTPCREL";
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if (needCloseParen) {
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needCloseParen = false;
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O << ')';
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}
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// Use rip when possible to reduce code size, except when
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// index or base register are also part of the address. e.g.
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// foo(%rip)(%rcx,%rax,4) is not legal
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O << "(%rip)";
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}
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}
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if (needCloseParen)
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O << ')';
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return;
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}
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case MachineOperand::MO_ExternalSymbol: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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bool needCloseParen = false;
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std::string Name(TAI->getGlobalPrefix());
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Name += MO.getSymbolName();
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if (isCallOp && printStub(TM, Subtarget)) {
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FnStubs.insert(Name);
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O << TAI->getPrivateGlobalPrefix() << Name << "$stub";
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return;
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}
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if (!isCallOp)
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O << '$';
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else if (Name[0] == '$') {
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// The name begins with a dollar-sign. In order to avoid having it look
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// like an integer immediate to the assembler, enclose it in parens.
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O << '(';
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needCloseParen = true;
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}
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O << Name;
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if (printGOT(TM, Subtarget)) {
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std::string GOTName(TAI->getGlobalPrefix());
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GOTName+="_GLOBAL_OFFSET_TABLE_";
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if (Name == GOTName)
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// HACK! Emit extra offset to PC during printing GOT offset to
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// compensate for the size of popl instruction. The resulting code
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// should look like:
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// call .piclabel
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// piclabel:
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// popl %some_register
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// addl $_GLOBAL_ADDRESS_TABLE_ + [.-piclabel], %some_register
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O << " + [.-"
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<< computePICLabel(getFunctionNumber(), TAI, Subtarget) << "]";
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if (isCallOp)
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O << "@PLT";
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}
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if (needCloseParen)
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O << ')';
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if (!isCallOp && Subtarget->isPICStyleRIPRel())
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O << "(%rip)";
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return;
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}
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default:
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O << "<unknown operand type>"; return;
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}
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}
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void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
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unsigned char value = MI->getOperand(Op).getImmedValue();
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assert(value <= 7 && "Invalid ssecc argument!");
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switch (value) {
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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}
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}
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void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
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const char *Modifier){
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assert(isMem(MI, Op) && "Invalid memory reference!");
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MachineOperand BaseReg = MI->getOperand(Op);
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MachineOperand IndexReg = MI->getOperand(Op+2);
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const MachineOperand &DispSpec = MI->getOperand(Op+3);
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bool NotRIPRel = IndexReg.getReg() || BaseReg.getReg();
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if (DispSpec.isGlobalAddress() ||
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DispSpec.isConstantPoolIndex() ||
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DispSpec.isJumpTableIndex()) {
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printOperand(MI, Op+3, "mem", NotRIPRel);
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} else {
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int DispVal = DispSpec.getImmedValue();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
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O << DispVal;
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}
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if (IndexReg.getReg() || BaseReg.getReg()) {
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unsigned ScaleVal = MI->getOperand(Op+1).getImmedValue();
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unsigned BaseRegOperand = 0, IndexRegOperand = 2;
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// There are cases where we can end up with ESP/RSP in the indexreg slot.
|
|
// If this happens, swap the base/index register to support assemblers that
|
|
// don't work when the index is *SP.
|
|
if (IndexReg.getReg() == X86::ESP || IndexReg.getReg() == X86::RSP) {
|
|
assert(ScaleVal == 1 && "Scale not supported for stack pointer!");
|
|
std::swap(BaseReg, IndexReg);
|
|
std::swap(BaseRegOperand, IndexRegOperand);
|
|
}
|
|
|
|
O << "(";
|
|
if (BaseReg.getReg())
|
|
printOperand(MI, Op+BaseRegOperand, Modifier);
|
|
|
|
if (IndexReg.getReg()) {
|
|
O << ",";
|
|
printOperand(MI, Op+IndexRegOperand, Modifier);
|
|
if (ScaleVal != 1)
|
|
O << "," << ScaleVal;
|
|
}
|
|
O << ")";
|
|
}
|
|
}
|
|
|
|
void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
|
|
std::string label = computePICLabel(getFunctionNumber(), TAI, Subtarget);
|
|
O << label << "\n" << label << ":";
|
|
}
|
|
|
|
|
|
bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
|
|
const char Mode) {
|
|
const MRegisterInfo &RI = *TM.getRegisterInfo();
|
|
unsigned Reg = MO.getReg();
|
|
switch (Mode) {
|
|
default: return true; // Unknown mode.
|
|
case 'b': // Print QImode register
|
|
Reg = getX86SubSuperRegister(Reg, MVT::i8);
|
|
break;
|
|
case 'h': // Print QImode high register
|
|
Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
|
|
break;
|
|
case 'w': // Print HImode register
|
|
Reg = getX86SubSuperRegister(Reg, MVT::i16);
|
|
break;
|
|
case 'k': // Print SImode register
|
|
Reg = getX86SubSuperRegister(Reg, MVT::i32);
|
|
break;
|
|
}
|
|
|
|
O << '%';
|
|
for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
|
|
O << (char)tolower(*Name);
|
|
return false;
|
|
}
|
|
|
|
/// PrintAsmOperand - Print out an operand for an inline asm expression.
|
|
///
|
|
bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
|
|
unsigned AsmVariant,
|
|
const char *ExtraCode) {
|
|
// Does this asm operand have a single letter operand modifier?
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
|
|
|
switch (ExtraCode[0]) {
|
|
default: return true; // Unknown modifier.
|
|
case 'c': // Don't print "$" before a global var name or constant.
|
|
printOperand(MI, OpNo, "mem");
|
|
return false;
|
|
case 'b': // Print QImode register
|
|
case 'h': // Print QImode high register
|
|
case 'w': // Print HImode register
|
|
case 'k': // Print SImode register
|
|
if (MI->getOperand(OpNo).isReg())
|
|
return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
|
|
printOperand(MI, OpNo);
|
|
return false;
|
|
|
|
case 'P': // Don't print @PLT, but do print as memory.
|
|
printOperand(MI, OpNo, "mem");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
printOperand(MI, OpNo);
|
|
return false;
|
|
}
|
|
|
|
bool X86ATTAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
unsigned OpNo,
|
|
unsigned AsmVariant,
|
|
const char *ExtraCode) {
|
|
if (ExtraCode && ExtraCode[0])
|
|
return true; // Unknown modifier.
|
|
printMemReference(MI, OpNo);
|
|
return false;
|
|
}
|
|
|
|
/// printMachineInstruction -- Print out a single X86 LLVM instruction
|
|
/// MI in AT&T syntax to the current output stream.
|
|
///
|
|
void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
|
|
++EmittedInsts;
|
|
|
|
// See if a truncate instruction can be turned into a nop.
|
|
switch (MI->getOpcode()) {
|
|
default: break;
|
|
case X86::PsMOVZX64rr32:
|
|
O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
|
|
break;
|
|
}
|
|
|
|
// Call the autogenerated instruction printer routines.
|
|
printInstruction(MI);
|
|
}
|
|
|
|
// Include the auto-generated portion of the assembly writer.
|
|
#include "X86GenAsmWriter.inc"
|
|
|