mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 16:31:16 +00:00
0225d5a3af
Without this change nothing was covering this addFrameMove:
// For 64-bit SVR4 when we have spilled CRs, the spill location
// is SP+8, not a frame-relative slot.
if (Subtarget.isSVR4ABI()
&& Subtarget.isPPC64()
&& (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
MachineLocation CSDst(PPC::X1, 8);
MachineLocation CSSrc(PPC::CR2);
MMI.addFrameMove(Label, CSDst, CSSrc);
continue;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181976 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.7 KiB
LLVM
63 lines
1.7 KiB
LLVM
; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
|
|
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64
|
|
|
|
declare void @foo()
|
|
|
|
define i32 @test_cr2() nounwind uwtable {
|
|
entry:
|
|
%ret = alloca i32, align 4
|
|
%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
|
|
store i32 %0, i32* %ret, align 4
|
|
call void @foo()
|
|
%1 = load i32* %ret, align 4
|
|
ret i32 %1
|
|
}
|
|
|
|
; PPC32: stw 31, -4(1)
|
|
; PPC32: stwu 1, -32(1)
|
|
; PPC32: mfcr 12
|
|
; PPC32-NEXT: stw 12, 24(31)
|
|
; PPC32: lwz 12, 24(31)
|
|
; PPC32-NEXT: mtcrf 32, 12
|
|
|
|
; PPC64: .cfi_startproc
|
|
; PPC64: mfcr 12
|
|
; PPC64: stw 12, 8(1)
|
|
; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
|
|
; PPC64: .cfi_def_cfa_offset 128
|
|
; PPC64: .cfi_offset lr, 16
|
|
; PPC64: .cfi_offset cr2, 8
|
|
; PPC64: addi 1, 1, [[AMT]]
|
|
; PPC64: lwz 12, 8(1)
|
|
; PPC64: mtcrf 32, 12
|
|
; PPC64: .cfi_endproc
|
|
|
|
define i32 @test_cr234() nounwind {
|
|
entry:
|
|
%ret = alloca i32, align 4
|
|
%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
|
|
store i32 %0, i32* %ret, align 4
|
|
call void @foo()
|
|
%1 = load i32* %ret, align 4
|
|
ret i32 %1
|
|
}
|
|
|
|
; PPC32: stw 31, -4(1)
|
|
; PPC32: stwu 1, -32(1)
|
|
; PPC32: mfcr 12
|
|
; PPC32-NEXT: stw 12, 24(31)
|
|
; PPC32: lwz 12, 24(31)
|
|
; PPC32-NEXT: mtcrf 32, 12
|
|
; PPC32-NEXT: mtcrf 16, 12
|
|
; PPC32-NEXT: mtcrf 8, 12
|
|
|
|
; PPC64: mfcr 12
|
|
; PPC64: stw 12, 8(1)
|
|
; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
|
|
; PPC64: addi 1, 1, [[AMT]]
|
|
; PPC64: lwz 12, 8(1)
|
|
; PPC64: mtcrf 32, 12
|
|
; PPC64: mtcrf 16, 12
|
|
; PPC64: mtcrf 8, 12
|
|
|