Kevin Enderby 46d7de7a19 Update the X86 disassembler to use xacquire and xrelease when appropriate. ... This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184490 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-20 22:32:18 +00:00
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AArch64	AArch64: print relocation addends if present on AArch64	2013-06-17 03:03:06 +00:00
ARM	This reverts r155000.	2013-06-20 17:42:36 +00:00
AsmParser
COFF
Disassembler	Update the X86 disassembler to use xacquire and xrelease when appropriate.	2013-06-20 22:32:18 +00:00
ELF	[MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives	2013-06-19 21:27:27 +00:00
MachO
Markup
MBlaze
Mips	Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers.	2013-06-20 11:21:49 +00:00
PowerPC	[MC] Support @ variants with directional labels	2013-06-20 16:24:17 +00:00
SystemZ	[SystemZ] Immediate compare-and-branch support	2013-05-29 11:58:52 +00:00
X86	Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.	2013-06-18 17:08:10 +00:00