Tim Northover 848d812931 ARM & AArch64: teach LowerVSETCC that output type size may differ from input. ... While various DAG combines try to guarantee that a vector SETCC operation will have the same output size as input, there's nothing intrinsic to either creation or LegalizeTypes that actually guarantees it, so the function needs to be ready to handle a mismatch. Fortunately this is easy enough, just extend or truncate the naturally compared result. I couldn't reproduce the failure in other backends that I know have SIMD, so it's probably only an issue for these two due to shared heritage. Should fix PR21645. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228518 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-08 00:50:47 +00:00
..
AArch64	ARM & AArch64: teach LowerVSETCC that output type size may differ from input.	2015-02-08 00:50:47 +00:00
ARM	ARM & AArch64: teach LowerVSETCC that output type size may differ from input.	2015-02-08 00:50:47 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	[PowerPC] Handle loop predecessor invokes	2015-02-07 07:32:58 +00:00
R600	R600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders	2015-02-06 02:51:29 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[X86][AVX2] AVX2 integer stack folding tests.	2015-02-07 23:28:16 +00:00
XCore