Elena Demikhovsky 8499a501e4 Scalarizer for masked load and store intrinsics. ... Masked vector intrinsics are a part of common LLVM IR, but they are really supported on AVX2 and AVX-512 targets. I added a code that translates masked intrinsic for all other targets. The masked vector intrinsic is converted to a chain of scalar operations inside conditional basic blocks. http://reviews.llvm.org/D6436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224897 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-28 08:54:45 +00:00
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AArch64	Lower multiply-negate operation to mneg on AArch64	2014-12-22 13:38:58 +00:00
ARM	[ARM] Don't break alignment when combining base updates into load/stores.	2014-12-23 06:07:31 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Reapplying 224775 load words.	2014-12-23 20:02:16 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Mips	[mips][microMIPS] Fix bugs related to atomic SC/LL instructions	2014-12-18 16:39:29 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	PowerPC: CTR shouldn't fire if a TLS call is in the loop	2014-12-27 19:45:38 +00:00
R600	Enable (sext x) == C --> x == (trunc C) combine	2014-12-21 16:48:42 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
X86	Scalarizer for masked load and store intrinsics.	2014-12-28 08:54:45 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00