Andrew Trick 84b454d1a2 misched preparation: modularize schedule emission. ...

ScheduleDAG has nothing to do with how the instructions are scheduled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8

2012-03-07 05:21:44 +00:00

..

Analysis

No functionality change. Type::isSized() can be expensive, so avoid calling it

2012-03-07 02:27:53 +00:00

Archive

Avoid using an invalidated iterator.

2012-01-23 05:07:16 +00:00

AsmParser

Convert assert(0) to llvm_unreachable

2012-02-07 05:05:23 +00:00

Bitcode

BitstreamWriter: Change primary output buffer to be a SmallVector instead of an

2012-02-29 20:31:09 +00:00

CodeGen

misched preparation: modularize schedule emission.

2012-03-07 05:21:44 +00:00

DebugInfo

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ExecutionEngine

Fixed the 32-bit runtime dynamic loader to allocate

2012-03-01 00:15:29 +00:00

Linker

Include cctype for isdigit. Patch by Stephen Hines.

2012-03-03 09:36:58 +00:00

MC

Make MCRegisterInfo available to the the MCInstPrinter.

2012-03-05 19:33:20 +00:00

Object

[Object]

2012-03-01 22:19:54 +00:00

Support

Added -view-background to avoid waiting for each GraphViz invocation.

2012-03-07 00:18:27 +00:00

TableGen

Switch the TableGen record's string-based DenseMap key to use the new

2012-03-05 10:36:16 +00:00

Target

ARM pre-v6 assembly parsing for umull/smull.

2012-03-07 01:09:17 +00:00

Transforms

fix typos

2012-03-05 17:39:47 +00:00

VMCore

Switch this code to use hash_combine_range rather than incremental calls

2012-03-07 03:22:32 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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