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84bc5427d6
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
4.9 KiB
C++
119 lines
4.9 KiB
C++
//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include <vector>
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namespace llvm {
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/// MachineRegisterInfo - Keep track of information for each virtual register,
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/// including its register class.
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class MachineRegisterInfo {
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/// VRegInfo - Information we keep for each virtual register. The entries in
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/// this vector are actually converted to vreg numbers by adding the
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/// MRegisterInfo::FirstVirtualRegister delta to their index.
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std::vector<const TargetRegisterClass*> VRegInfo;
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/// UsedPhysRegs - This is a bit vector that is computed and set by the
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/// register allocator, and must be kept up to date by passes that run after
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/// register allocation (though most don't modify this). This is used
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/// so that the code generator knows which callee save registers to save and
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/// for other target specific uses.
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BitVector UsedPhysRegs;
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/// LiveIns/LiveOuts - Keep track of the physical registers that are
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/// livein/liveout of the function. Live in values are typically arguments in
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/// registers, live out values are typically return values in registers.
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/// LiveIn values are allowed to have virtual registers associated with them,
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/// stored in the second element.
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std::vector<std::pair<unsigned, unsigned> > LiveIns;
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std::vector<unsigned> LiveOuts;
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public:
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MachineRegisterInfo(const MRegisterInfo &MRI);
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//===--------------------------------------------------------------------===//
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// Virtual Register Info
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//===--------------------------------------------------------------------===//
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/// getRegClass - Return the register class of the specified virtual register.
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const TargetRegisterClass *getRegClass(unsigned Reg) {
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Reg -= MRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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return VRegInfo[Reg];
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}
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
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assert(RegClass && "Cannot create register without RegClass!");
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VRegInfo.push_back(RegClass);
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return getLastVirtReg();
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}
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/// getLastVirtReg - Return the highest currently assigned virtual register.
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///
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unsigned getLastVirtReg() const {
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return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
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}
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//===--------------------------------------------------------------------===//
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// Physical Register Use Info
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//===--------------------------------------------------------------------===//
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/// isPhysRegUsed - Return true if the specified register is used in this
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/// function. This only works after register allocation.
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bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
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/// setPhysRegUsed - Mark the specified register used in this function.
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/// This should only be called during and after register allocation.
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void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
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/// setPhysRegUnused - Mark the specified register unused in this function.
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/// This should only be called during and after register allocation.
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void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
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//===--------------------------------------------------------------------===//
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// LiveIn/LiveOut Management
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//===--------------------------------------------------------------------===//
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/// addLiveIn/Out - Add the specified register as a live in/out. Note that it
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/// is an error to add the same register to the same set more than once.
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void addLiveIn(unsigned Reg, unsigned vreg = 0) {
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LiveIns.push_back(std::make_pair(Reg, vreg));
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}
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void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
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// Iteration support for live in/out sets. These sets are kept in sorted
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// order by their register number.
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typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
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livein_iterator;
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typedef std::vector<unsigned>::const_iterator liveout_iterator;
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livein_iterator livein_begin() const { return LiveIns.begin(); }
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livein_iterator livein_end() const { return LiveIns.end(); }
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bool livein_empty() const { return LiveIns.empty(); }
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liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
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liveout_iterator liveout_end() const { return LiveOuts.end(); }
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bool liveout_empty() const { return LiveOuts.empty(); }
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};
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} // End llvm namespace
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#endif
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