llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-03 08:55:51 +00:00

History

Rafael Espindola 6880f0e19f Fix PR18743. The IR @foo = private constant i32 42 is valid, but before this patch we would produce an invalid MachO from it. It was invalid because it would use an L label in a section where the liker needs the labels in order to atomize it. One way of fixing it would be to just reject this IR in the backend, but that would not be very front end friendly. What this patch does is use an 'l' prefix in sections that we know the linker requires symbols for atomizing them. This allows frontends to just use private and not worry about which sections they go to or how the linker handles them. One small issue with this strategy is that now a symbol name depends on the section, which is not available before codegen. This is not a problem in practice. The reason is that it only happens with private linkage, which will be ignored by the non codegen users (llvm-nm and llvm-ar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201608 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-18 22:24:57 +00:00
..
AsmParser	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
Disassembler	[Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.	2014-01-12 04:34:31 +00:00
InstPrinter	[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.	2014-02-07 02:36:06 +00:00
MCTargetDesc	Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call	2014-02-13 14:44:26 +00:00
TargetInfo
CMakeLists.txt	[Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.	2014-01-29 04:51:35 +00:00
DelaySlotFiller.cpp	[Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.	2014-01-11 19:38:03 +00:00
LLVMBuild.txt	[Sparc] Add initial implementation of disassembler for sparc	2014-01-06 08:08:58 +00:00
Makefile	[Sparc] Add initial implementation of disassembler for sparc	2014-01-06 08:08:58 +00:00
README.txt
Sparc.h
Sparc.td	Only generate the popc instruction for SPARC CPUs that implement it.	2014-01-26 06:09:59 +00:00
SparcAsmPrinter.cpp	[Sparc] Emit correct relocations for PIC code when integrated assembler is used.	2014-02-07 04:24:35 +00:00
SparcCallingConv.td	The SPARCv9 ABI returns a float in %f0.	2014-01-12 04:13:17 +00:00
SparcCodeEmitter.cpp	[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.	2014-02-07 02:36:06 +00:00
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstr64Bit.td	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
SparcInstrAliases.td	[Sparc] Add support for parsing synthetic instruction 'mov'.	2014-02-07 09:06:52 +00:00
SparcInstrFormats.td	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
SparcInstrInfo.cpp	[SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9.	2014-01-29 03:35:08 +00:00
SparcInstrInfo.h
SparcInstrInfo.td	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp	[Sparc] Emit correct relocations for PIC code when integrated assembler is used.	2014-02-07 04:24:35 +00:00
SparcISelLowering.h	Implement atomicrmw operations in 32 and 64 bits for SPARCv9.	2014-01-24 06:23:31 +00:00
SparcJITInfo.cpp	[Sparc] Save and restore float registers that may be used for parameter passing.	2014-01-31 01:53:08 +00:00
SparcJITInfo.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp	[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.	2014-02-07 02:36:06 +00:00
SparcRegisterInfo.cpp	[Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.	2014-02-01 18:54:16 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcRelocations.h	[SparcV9] Add support for JIT in Sparc64.	2014-01-24 07:10:19 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp	Clean up the Legal/Expand logic for SPARC popc.	2014-01-26 08:12:34 +00:00
SparcSubtarget.h	Only generate the popc instruction for SPARC CPUs that implement it.	2014-01-26 06:09:59 +00:00
SparcTargetMachine.cpp
SparcTargetMachine.h
SparcTargetObjectFile.cpp	Fix PR18743.	2014-02-18 22:24:57 +00:00
SparcTargetObjectFile.h	Fix PR18743.	2014-02-18 22:24:57 +00:00
SparcTargetStreamer.h	Construct the MCStreamer before constructing the MCTargetStreamer.	2014-01-26 06:06:37 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.