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https://github.com/c64scene-ar/llvm-6502.git
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4b5324ad2c
optimized x86-64 (and x86) calls so that they work (... at least for my test cases). Should fix the following problems: Problem 1: When i introduced the optimized handling of arguments for tail called functions (using a sequence of copyto/copyfrom virtual registers instead of always lowering to top of the stack) i did not handle byval arguments correctly e.g they did not work at all :). Problem 2: On x86-64 after the arguments of the tail called function are moved to their registers (which include ESI/RSI etc), tail call optimization performs byval lowering which causes xSI,xDI, xCX registers to be overwritten. This is handled in this patch by moving the arguments to virtual registers first and after the byval lowering the arguments are moved from those virtual registers back to RSI/RDI/RCX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49584 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.4 KiB
LLVM
30 lines
1.4 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep TAILCALL
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; Expect 2 rep;movs because of tail call byval lowering.
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; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep rep | wc -l | grep 2
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; A sequence of copyto/copyfrom virtual registers is used to deal with byval
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; lowering appearing after moving arguments to registers. The following two
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; checks verify that the register allocator changes those sequences to direct
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; moves to argument register where it can (for registers that are not used in
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; byval lowering - not rsi, not rdi, not rcx).
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; Expect argument 4 to be moved directly to register edx.
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; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep movl | grep {7} | grep edx
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; Expect argument 6 to be moved directly to register r8.
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; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep movl | grep {17} | grep r8
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%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,
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i64, i64, i64, i64, i64, i64, i64, i64,
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i64, i64, i64, i64, i64, i64, i64, i64 }
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declare fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5)
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define fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) {
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entry:
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%tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
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%tmp3 = load i64* %tmp2, align 8
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%tmp4 = tail call fastcc i64 @tailcallee(%struct.s* %a byval, i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
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ret i64 %tmp4
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}
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