mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
48575f6ea7
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
349 lines
17 KiB
LLVM
349 lines
17 KiB
LLVM
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
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; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
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%struct.int16x8_t = type { <8 x i16> }
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%struct.int32x4_t = type { <4 x i32> }
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
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define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
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entry:
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; CHECK: t1:
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; CHECK: vld1.16
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; CHECK-NOT: vmov d
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; CHECK: vmovl.s16
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; CHECK: vshrn.i32
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; CHECK: vshrn.i32
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; CHECK-NOT: vmov d
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; CHECK-NEXT: vst1.16
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%0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
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%1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
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%2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
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%3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1]
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%4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1]
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%5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
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%6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2]
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%7 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1]
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%8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1]
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%9 = sext <4 x i16> %8 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%10 = extractelement <2 x double> %6, i32 1 ; <double> [#uses=1]
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%11 = bitcast double %10 to <4 x i16> ; <<4 x i16>> [#uses=1]
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%12 = sext <4 x i16> %11 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1]
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%14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1]
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%15 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %13, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1]
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%16 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %14, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1]
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%17 = shufflevector <4 x i16> %15, <4 x i16> %16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1]
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%18 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17, i32 1)
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ret void
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}
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define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
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entry:
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; CHECK: t2:
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; CHECK: vld1.16
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; CHECK-NOT: vmov
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; CHECK: vmul.i16
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; CHECK: vld1.16
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; CHECK: vmul.i16
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; CHECK-NOT: vmov
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; CHECK: vst1.16
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; CHECK: vst1.16
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%0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
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%1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1]
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%2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
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%3 = load <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1]
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%4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1]
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%5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
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%6 = getelementptr inbounds i16* %i_ptr, i32 8 ; <i16*> [#uses=1]
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%7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1]
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%8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1]
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%9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1]
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%10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1]
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%11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1)
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%12 = getelementptr inbounds i16* %o_ptr, i32 8 ; <i16*> [#uses=1]
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%13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1)
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ret void
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}
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define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
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; CHECK: t3:
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; CHECK: vld3.8
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; CHECK: vmul.i8
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; CHECK: vmov r
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; CHECK-NOT: vmov d
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; CHECK: vst3.8
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%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
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%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1]
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1]
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%tmp5 = sub <8 x i8> %tmp3, %tmp4
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%tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1]
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%tmp7 = mul <8 x i8> %tmp4, %tmp2
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tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)
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ret <8 x i8> %tmp4
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}
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define void @t4(i32* %in, i32* %out) nounwind {
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entry:
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; CHECK: t4:
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; CHECK: vld2.32
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; CHECK-NOT: vmov
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; CHECK: vld2.32
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; CHECK-NOT: vmov
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; CHECK: bne
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%tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1]
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%tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
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%tmp3 = getelementptr inbounds i32* %in, i32 8 ; <i32*> [#uses=1]
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%tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1]
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%tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
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%tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1]
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br i1 undef, label %return1, label %return2
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return1:
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; CHECK: %return1
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; CHECK-NOT: vmov
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; CHECK-NEXT: vadd.i32
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; CHECK-NEXT: vadd.i32
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; CHECK-NEXT: vst2.32
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%tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
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%tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1]
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%tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1]
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%tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
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%tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1]
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%tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1]
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tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1)
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ret void
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return2:
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; CHECK: %return2
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; CHECK: vadd.i32
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; CHECK: vmov q9, q11
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; CHECK-NOT: vmov
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; CHECK: vst2.32 {d16, d17, d18, d19}
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%tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
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%tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
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%tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1]
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tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1)
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call void @llvm.trap()
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unreachable
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}
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define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
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; CHECK: t5:
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; CHECK: vldmia
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; CHECK: vmov q9, q8
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; CHECK-NOT: vmov
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; CHECK: vld2.16 {d16[1], d18[1]}, [r0]
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; CHECK-NOT: vmov
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; CHECK: vadd.i16
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%tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1]
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%tmp1 = load <8 x i16>* %B ; <<8 x i16>> [#uses=2]
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%tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]
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%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1]
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%tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1]
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%tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp5
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}
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define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
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; CHECK: t6:
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; CHECK: vldr.64
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; CHECK: vmov d17, d16
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; CHECK-NEXT: vld2.8 {d16[1], d17[1]}
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%tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2]
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%tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1]
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%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1]
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%tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1]
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ret <8 x i8> %tmp5
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}
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define void @t7(i32* %iptr, i32* %optr) nounwind {
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entry:
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; CHECK: t7:
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; CHECK: vld2.32
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; CHECK: vst2.32
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; CHECK: vld1.32 {d16, d17},
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; CHECK: vmov q9, q8
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; CHECK-NOT: vmov
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; CHECK: vuzp.32 q8, q9
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; CHECK: vst1.32
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%0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2]
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%1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
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%tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1]
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%tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1]
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%2 = bitcast i32* %optr to i8* ; <i8*> [#uses=2]
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tail call void @llvm.arm.neon.vst2.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)
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%3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %0, i32 1) ; <<4 x i32>> [#uses=1]
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%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v4i32(i8* %2, <4 x i32> %4, i32 1)
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ret void
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}
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; PR7156
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define arm_aapcs_vfpcc i32 @t8() nounwind {
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; CHECK: t8:
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; CHECK: vrsqrte.f32 q8, q8
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bb.nph55.bb.nph55.split_crit_edge:
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br label %bb3
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bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
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br i1 undef, label %bb5, label %bb3
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bb5: ; preds = %bb3
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br label %bb.i25
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bb.i25: ; preds = %bb.i25, %bb5
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%0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
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%1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1]
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%2 = fmul <4 x float> %1, undef ; <<4 x float>> [#uses=1]
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%3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1]
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%tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]
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%4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1]
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%5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1]
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%6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1]
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store float %6, float* undef, align 4
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br i1 undef, label %bb6, label %bb.i25
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bb6: ; preds = %bb.i25
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br i1 undef, label %bb7, label %bb14
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bb7: ; preds = %bb6
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br label %bb.i49
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bb.i49: ; preds = %bb.i49, %bb7
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br i1 undef, label %bb.i19, label %bb.i49
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bb.i19: ; preds = %bb.i19, %bb.i49
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br i1 undef, label %exit, label %bb.i19
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exit: ; preds = %bb.i19
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unreachable
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bb14: ; preds = %bb6
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ret i32 0
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}
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%0 = type { %1, %1, %1, %1 }
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%1 = type { %2 }
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%2 = type { <4 x float> }
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%3 = type { %0, %1 }
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; PR7157
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define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
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; CHECK: t9:
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; CHECK: vldr.64
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; CHECK-NOT: vmov d{{.*}}, d16
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; CHECK: vmov.i32 d17
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; CHECK-NEXT: vstmia r0, {d16, d17}
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; CHECK-NEXT: vstmia r0, {d16, d17}
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%3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
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%4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
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store <4 x float> %4, <4 x float>* undef, align 16
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%5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
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store <4 x float> %5, <4 x float>* undef, align 16
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br label %8
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; <label>:6 ; preds = %8
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br label %7
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; <label>:7 ; preds = %6
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br label %8
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; <label>:8 ; preds = %7, %2
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br label %6
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; <label>:9 ; preds = %8
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ret float undef
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; <label>:10 ; preds = %6
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ret float 9.990000e+02
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}
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; PR7162
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define arm_aapcs_vfpcc i32 @t10() nounwind {
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entry:
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; CHECK: t10:
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; CHECK: vmul.f32 q8, q8, d0[0]
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; CHECK: vmov.i32 q9, #0x3F000000
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; CHECK: vadd.f32 q8, q8, q8
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%0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1]
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%2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1]
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%3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
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%tmp54.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]
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%4 = extractelement <2 x double> %tmp54.i, i32 1 ; <double> [#uses=1]
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%5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1]
|
|
%6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
|
|
%7 = fmul <4 x float> undef, %6 ; <<4 x float>> [#uses=1]
|
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%8 = fadd <4 x float> %7, undef ; <<4 x float>> [#uses=1]
|
|
%9 = fadd <4 x float> %8, undef ; <<4 x float>> [#uses=1]
|
|
%10 = shufflevector <4 x float> undef, <4 x float> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1]
|
|
%11 = fmul <4 x float> %10, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
|
|
%12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
|
|
%13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
|
|
%14 = fmul <4 x float> %13, undef ; <<4 x float>> [#uses=1]
|
|
%15 = fadd <4 x float> undef, %14 ; <<4 x float>> [#uses=1]
|
|
%16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
|
|
%17 = fmul <4 x float> %16, undef ; <<4 x float>> [#uses=1]
|
|
%18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1]
|
|
store float %18, float* undef, align 4
|
|
br i1 undef, label %exit, label %bb14
|
|
|
|
exit: ; preds = %bb.i19
|
|
unreachable
|
|
|
|
bb14: ; preds = %bb6
|
|
ret i32 0
|
|
}
|
|
|
|
; This test crashes the coalescer because live variables were not updated properly.
|
|
define <8 x i8> @t11(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind {
|
|
%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
|
|
%tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1]
|
|
%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
|
|
%tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1]
|
|
%tmp2bd = add <8 x i8> zeroinitializer, %tmp2d ; <<8 x i8>> [#uses=1]
|
|
%tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1]
|
|
%tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f ; <<8 x i8>> [#uses=1]
|
|
%tmp2efgh = mul <8 x i8> %tmp2ef, undef ; <<8 x i8>> [#uses=2]
|
|
call void @llvm.arm.neon.vst3.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1)
|
|
%tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd ; <<8 x i8>> [#uses=1]
|
|
%tmp7 = mul <8 x i8> undef, %tmp2 ; <<8 x i8>> [#uses=1]
|
|
tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1)
|
|
ret <8 x i8> undef
|
|
}
|
|
|
|
declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly
|
|
|
|
declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
|
|
|
|
declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind
|
|
|
|
declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind
|
|
|
|
declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32)
|
|
nounwind
|
|
|
|
declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
|
|
|
|
declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*, i32) nounwind readonly
|
|
|
|
declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
|
|
|
|
declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
|
|
|
|
declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind
|
|
|
|
declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
|
|
|
|
declare void @llvm.trap() nounwind
|