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https://github.com/c64scene-ar/llvm-6502.git
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Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
354 lines
13 KiB
C++
354 lines
13 KiB
C++
//===-- Passes.cpp - Target independent code generation passes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code
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// generation passes provided by the LLVM backend.
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//
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//===---------------------------------------------------------------------===//
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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cl::desc("Disable tail duplication"));
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static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
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cl::desc("Disable pre-register allocation tail duplication"));
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static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
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cl::Hidden, cl::desc("Enable probability-driven block placement"));
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static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
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cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
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static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
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cl::desc("Disable code placement"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
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cl::desc("Disable Machine Dead Code Elimination"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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cl::desc("Disable Machine Common Subexpression Elimination"));
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static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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cl::desc("Disable Copy Propagation pass"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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//===---------------------------------------------------------------------===//
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/// TargetPassConfig
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//===---------------------------------------------------------------------===//
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INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
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"Target Pass Configuration", false, false)
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char TargetPassConfig::ID = 0;
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// Out of line virtual method.
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TargetPassConfig::~TargetPassConfig() {}
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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: ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(false) {
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// Register all target independent codegen passes to activate their PassIDs,
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// including this pass itself.
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initializeCodeGen(*PassRegistry::getPassRegistry());
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}
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/// createPassConfig - Create a pass configuration object to be used by
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/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
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///
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/// Targets may override this to extend TargetPassConfig.
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TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(this, PM);
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}
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TargetPassConfig::TargetPassConfig()
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: ImmutablePass(ID), PM(*(PassManagerBase*)0) {
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llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
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}
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void TargetPassConfig::addCommonPass(char &ID) {
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// FIXME: about to be implemented.
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}
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void TargetPassConfig::printNoVerify(const char *Banner) const {
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if (TM->shouldPrintMachineCode())
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PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
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}
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void TargetPassConfig::printAndVerify(const char *Banner) const {
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if (TM->shouldPrintMachineCode())
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PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
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if (VerifyMachineCode)
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PM.add(createMachineVerifierPass(Banner));
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}
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/// Add common target configurable passes that perform LLVM IR to IR transforms
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/// following machine independent optimization.
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void TargetPassConfig::addIRPasses() {
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// Basic AliasAnalysis support.
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// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
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// BasicAliasAnalysis wins if they disagree. This is intended to help
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// support "obvious" type-punning idioms.
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PM.add(createTypeBasedAliasAnalysisPass());
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PM.add(createBasicAliasAnalysisPass());
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// Before running any passes, run the verifier to determine if the input
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// coming from the front-end and/or optimizer is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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// Run loop strength reduction before anything else.
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if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
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}
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PM.add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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}
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/// Add common passes that perform LLVM IR to IR transforms in preparation for
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/// instruction selection.
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void TargetPassConfig::addISelPrepare() {
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if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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addPreISel();
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if (PrintISelInput)
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PM.add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&dbgs()));
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// All passes which modify the LLVM IR are now complete; run the verifier
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// to ensure that the IR is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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}
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void TargetPassConfig::addMachinePasses() {
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// Print the instruction selected machine code...
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printAndVerify("After Instruction Selection");
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// Expand pseudo-instructions emitted by ISel.
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PM.add(createExpandISelPseudosPass());
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// Pre-ra tail duplication.
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if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
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PM.add(createTailDuplicatePass(true));
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printAndVerify("After Pre-RegAlloc TailDuplicate");
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}
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// Optimize PHIs before DCE: removing dead PHI cycles may make more
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// instructions dead.
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if (getOptLevel() != CodeGenOpt::None)
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PM.add(createOptimizePHIsPass());
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// If the target requests it, assign local variables to stack slots relative
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// to one another and simplify frame index references where possible.
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PM.add(createLocalStackSlotAllocationPass());
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if (getOptLevel() != CodeGenOpt::None) {
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// With optimization, dead code should already be eliminated. However
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// there is one known exception: lowered code for arguments that are only
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// used by tail calls, where the tail calls reuse the incoming stack
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// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
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if (!DisableMachineDCE)
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PM.add(createDeadMachineInstructionElimPass());
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printAndVerify("After codegen DCE pass");
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if (!DisableMachineLICM)
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PM.add(createMachineLICMPass());
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if (!DisableMachineCSE)
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PM.add(createMachineCSEPass());
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if (!DisableMachineSink)
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PM.add(createMachineSinkingPass());
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printAndVerify("After Machine LICM, CSE and Sinking passes");
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PM.add(createPeepholeOptimizerPass());
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printAndVerify("After codegen peephole optimization pass");
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}
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// Run pre-ra passes.
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if (addPreRegAlloc())
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printAndVerify("After PreRegAlloc passes");
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// Perform register allocation.
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PM.add(createRegisterAllocator(getOptLevel()));
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printAndVerify("After Register Allocation");
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// Perform stack slot coloring and post-ra machine LICM.
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if (getOptLevel() != CodeGenOpt::None) {
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// FIXME: Re-enable coloring with register when it's capable of adding
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// kill markers.
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if (!DisableSSC)
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PM.add(createStackSlotColoringPass(false));
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// Run post-ra machine LICM to hoist reloads / remats.
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if (!DisablePostRAMachineLICM)
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PM.add(createMachineLICMPass(false));
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printAndVerify("After StackSlotColoring and postra Machine LICM");
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}
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// Run post-ra passes.
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if (addPostRegAlloc())
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printAndVerify("After PostRegAlloc passes");
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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printAndVerify("After PrologEpilogCodeInserter");
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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printNoVerify("After BranchFolding");
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}
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// Tail duplication.
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if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
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PM.add(createTailDuplicatePass(false));
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printNoVerify("After TailDuplicate");
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}
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// Copy propagation.
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if (getOptLevel() != CodeGenOpt::None && !DisableCopyProp) {
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PM.add(createMachineCopyPropagationPass());
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printNoVerify("After copy propagation pass");
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}
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// Expand pseudo instructions before second scheduling pass.
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PM.add(createExpandPostRAPseudosPass());
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printNoVerify("After ExpandPostRAPseudos");
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// Run pre-sched2 passes.
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if (addPreSched2())
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printNoVerify("After PreSched2 passes");
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// Second pass scheduler.
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if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
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PM.add(createPostRAScheduler(getOptLevel()));
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printNoVerify("After PostRAScheduler");
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}
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PM.add(createGCMachineCodeAnalysisPass());
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if (PrintGCInfo)
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PM.add(createGCInfoPrinter(dbgs()));
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if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
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if (EnableBlockPlacement) {
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// MachineBlockPlacement is an experimental pass which is disabled by
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// default currently. Eventually it should subsume CodePlacementOpt, so
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// when enabled, the other is disabled.
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PM.add(createMachineBlockPlacementPass());
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printNoVerify("After MachineBlockPlacement");
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} else {
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PM.add(createCodePlacementOptPass());
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printNoVerify("After CodePlacementOpt");
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}
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// Run a separate pass to collect block placement statistics.
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if (EnableBlockPlacementStats) {
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PM.add(createMachineBlockPlacementStatsPass());
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printNoVerify("After MachineBlockPlacementStats");
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}
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}
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if (addPreEmitPass())
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printNoVerify("After PreEmit passes");
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}
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//===---------------------------------------------------------------------===//
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///
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/// RegisterRegAlloc class - Track the registration of register allocators.
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///
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//===---------------------------------------------------------------------===//
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MachinePassRegistry RegisterRegAlloc::Registry;
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static FunctionPass *createDefaultRegisterAllocator() { return 0; }
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static RegisterRegAlloc
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defaultRegAlloc("default",
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"pick register allocator based on -O option",
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createDefaultRegisterAllocator);
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//===---------------------------------------------------------------------===//
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///
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/// RegAlloc command line options.
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///
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//===---------------------------------------------------------------------===//
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static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
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RegisterPassParser<RegisterRegAlloc> >
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RegAlloc("regalloc",
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cl::init(&createDefaultRegisterAllocator),
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cl::desc("Register allocator to use"));
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//===---------------------------------------------------------------------===//
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///
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/// createRegisterAllocator - choose the appropriate register allocator.
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///
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//===---------------------------------------------------------------------===//
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FunctionPass *llvm::createRegisterAllocator(CodeGenOpt::Level OptLevel) {
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RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
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if (!Ctor) {
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Ctor = RegAlloc;
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RegisterRegAlloc::setDefault(RegAlloc);
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}
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if (Ctor != createDefaultRegisterAllocator)
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return Ctor();
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// When the 'default' allocator is requested, pick one based on OptLevel.
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switch (OptLevel) {
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case CodeGenOpt::None:
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return createFastRegisterAllocator();
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default:
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return createGreedyRegisterAllocator();
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}
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}
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