mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
272 lines
7.9 KiB
LLVM
272 lines
7.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vaddpd
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define <4 x double> @addpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
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entry:
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%add.i = fadd <4 x double> %x, %y
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ret <4 x double> %add.i
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}
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; CHECK: vaddpd LCP{{.*}}(%rip)
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define <4 x double> @addpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
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entry:
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%add.i = fadd <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
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ret <4 x double> %add.i
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}
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; CHECK: vaddps
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define <8 x float> @addps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
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entry:
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%add.i = fadd <8 x float> %x, %y
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ret <8 x float> %add.i
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}
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; CHECK: vaddps LCP{{.*}}(%rip)
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define <8 x float> @addps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
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entry:
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%add.i = fadd <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
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ret <8 x float> %add.i
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}
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; CHECK: vsubpd
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define <4 x double> @subpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
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entry:
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%sub.i = fsub <4 x double> %x, %y
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ret <4 x double> %sub.i
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}
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; CHECK: vsubpd (%
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define <4 x double> @subpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp {
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entry:
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%tmp2 = load <4 x double>* %x, align 32
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%sub.i = fsub <4 x double> %y, %tmp2
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ret <4 x double> %sub.i
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}
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; CHECK: vsubps
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define <8 x float> @subps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
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entry:
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%sub.i = fsub <8 x float> %x, %y
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ret <8 x float> %sub.i
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}
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; CHECK: vsubps (%
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define <8 x float> @subps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp {
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entry:
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%tmp2 = load <8 x float>* %x, align 32
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%sub.i = fsub <8 x float> %y, %tmp2
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ret <8 x float> %sub.i
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}
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; CHECK: vmulpd
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define <4 x double> @mulpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
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entry:
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%mul.i = fmul <4 x double> %x, %y
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ret <4 x double> %mul.i
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}
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; CHECK: vmulpd LCP{{.*}}(%rip)
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define <4 x double> @mulpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
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entry:
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%mul.i = fmul <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
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ret <4 x double> %mul.i
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}
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; CHECK: vmulps
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define <8 x float> @mulps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
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entry:
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%mul.i = fmul <8 x float> %x, %y
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ret <8 x float> %mul.i
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}
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; CHECK: vmulps LCP{{.*}}(%rip)
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define <8 x float> @mulps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
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entry:
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%mul.i = fmul <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
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ret <8 x float> %mul.i
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}
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; CHECK: vdivpd
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define <4 x double> @divpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
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entry:
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%div.i = fdiv <4 x double> %x, %y
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ret <4 x double> %div.i
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}
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; CHECK: vdivpd LCP{{.*}}(%rip)
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define <4 x double> @divpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
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entry:
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%div.i = fdiv <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
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ret <4 x double> %div.i
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}
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; CHECK: vdivps
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define <8 x float> @divps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
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entry:
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%div.i = fdiv <8 x float> %x, %y
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ret <8 x float> %div.i
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}
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; CHECK: vdivps LCP{{.*}}(%rip)
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define <8 x float> @divps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
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entry:
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%div.i = fdiv <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
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ret <8 x float> %div.i
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}
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; CHECK: vsqrtss
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define float @sqrtA(float %a) nounwind uwtable readnone ssp {
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entry:
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%conv1 = tail call float @sqrtf(float %a) nounwind readnone
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ret float %conv1
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}
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declare double @sqrt(double) readnone
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; CHECK: vsqrtsd
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define double @sqrtB(double %a) nounwind uwtable readnone ssp {
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entry:
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%call = tail call double @sqrt(double %a) nounwind readnone
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ret double %call
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}
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declare float @sqrtf(float) readnone
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpaddq %xmm
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; CHECK-NEXT: vpaddq %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = add <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpaddd %xmm
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; CHECK-NEXT: vpaddd %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = add <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpaddw %xmm
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; CHECK-NEXT: vpaddw %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = add <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpaddb %xmm
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; CHECK-NEXT: vpaddb %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = add <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpsubq %xmm
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; CHECK-NEXT: vpsubq %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = sub <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpsubd %xmm
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; CHECK-NEXT: vpsubd %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = sub <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpsubw %xmm
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; CHECK-NEXT: vpsubw %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = sub <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpsubb %xmm
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; CHECK-NEXT: vpsubb %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = sub <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpmulld %xmm
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; CHECK-NEXT: vpmulld %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = mul <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpmullw %xmm
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; CHECK-NEXT: vpmullw %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = mul <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vpmuludq %xmm
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; CHECK-NEXT: vpsrlq $32, %xmm
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; CHECK-NEXT: vpmuludq %xmm
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; CHECK-NEXT: vpsllq $32, %xmm
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; CHECK-NEXT: vpaddq %xmm
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; CHECK-NEXT: vpsrlq $32, %xmm
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; CHECK-NEXT: vpmuludq %xmm
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; CHECK-NEXT: vpsllq $32, %xmm
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; CHECK-NEXT: vpaddq %xmm
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; CHECK-NEXT: vpmuludq %xmm
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; CHECK-NEXT: vpsrlq $32, %xmm
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; CHECK-NEXT: vpmuludq %xmm
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; CHECK-NEXT: vpsllq $32, %xmm
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; CHECK-NEXT: vpaddq %xmm
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; CHECK-NEXT: vpsrlq $32, %xmm
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; CHECK-NEXT: vpmuludq %xmm
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; CHECK-NEXT: vpsllq $32, %xmm
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; CHECK-NEXT: vpaddq %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = mul <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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define <4 x float> @int_sqrt_ss() {
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; CHECK: int_sqrt_ss
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; CHECK: vsqrtss
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%x0 = load float addrspace(1)* undef, align 8
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%x1 = insertelement <4 x float> undef, float %x0, i32 0
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%x2 = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %x1) nounwind
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ret <4 x float> %x2
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}
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