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7cd7154421
parsing (and latent bug in the instruction definitions). This is effectively a revert of r136287 which tried to address a specific and narrow case of immediate operands failing to be accepted by x86 instructions with a pretty heavy hammer: it introduced a new kind of operand that behaved differently. All of that is removed with this commit, but the test cases are both preserved and enhanced. The core problem that r136287 and this commit are trying to handle is that gas accepts both of the following instructions: insertps $192, %xmm0, %xmm1 insertps $-64, %xmm0, %xmm1 These will encode to the same byte sequence, with the immediate occupying an 8-bit entry. The first form was fixed by r136287 but that broke the prior handling of the second form! =[ Ironically, we would still emit the second form in some cases and then be unable to re-assemble the output. The reason why the first instruction failed to be handled is because prior to r136287 the operands ere marked 'i32i8imm' which forces them to be sign-extenable. Clearly, that won't work for 192 in a single byte. However, making thim zero-extended or "unsigned" doesn't really address the core issue either because it breaks negative immediates. The correct fix is to make these operands 'i8imm' reflecting that they can be either signed or unsigned but must be 8-bit immediates. This patch backs out r136287 and then changes those places as well as some others to use 'i8imm' rather than one of the extended variants. Naturally, this broke something else. The custom DAG nodes had to be updated to have a much more accurate type constraint of an i8 node, and a bunch of Pat immediates needed to be specified as i8 values. The fallout didn't end there though. We also then ceased to be able to match the instruction-specific intrinsics to the instructions so modified. Digging, this is because they too used i32 rather than i8 in their signature. So I've also switched those intrinsics to i8 arguments in line with the instructions. In order to make the intrinsic adjustments of course, I also had to add auto upgrading for the intrinsics. I suspect that the intrinsic argument types may have led everything down this rabbit hole. Pretty happy with the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217310 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
5.5 KiB
LLVM
137 lines
5.5 KiB
LLVM
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=X32 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=X64 --check-prefix=CHECK
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define <4 x i32> @blendvb_fallback_v4i32(<4 x i1> %mask, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @blendvb_fallback_v4i32
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; CHECK: vblendvps
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; CHECK: ret
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%ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %ret
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}
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define <8 x i32> @blendvb_fallback_v8i32(<8 x i1> %mask, <8 x i32> %x, <8 x i32> %y) {
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; CHECK-LABEL: @blendvb_fallback_v8i32
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; CHECK: vblendvps
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; CHECK: ret
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%ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %ret
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}
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define <8 x float> @blendvb_fallback_v8f32(<8 x i1> %mask, <8 x float> %x, <8 x float> %y) {
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; CHECK-LABEL: @blendvb_fallback_v8f32
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; CHECK: vblendvps
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; CHECK: ret
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%ret = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
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ret <8 x float> %ret
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; CHECK-LABEL: insertps_from_vector_load:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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%1 = load <4 x float>* %pb, align 16
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%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
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ret <4 x float> %2
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}
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;; Use a non-zero CountS for insertps
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define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; CHECK-LABEL: insertps_from_vector_load_offset:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; CHECK-NOT: mov
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;; Try to match a bit more of the instr, since we need the load's offset.
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; CHECK: insertps $96, 4(%{{...}}), %
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; CHECK-NEXT: ret
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%1 = load <4 x float>* %pb, align 16
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%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
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ret <4 x float> %2
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}
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define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
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; CHECK-LABEL: insertps_from_vector_load_offset_2:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; X32: movl 8(%esp), %ecx
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; CHECK-NOT: mov
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;; Try to match a bit more of the instr, since we need the load's offset.
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; CHECK: vinsertps $-64, 12(%{{...}},%{{...}}), %
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; CHECK-NEXT: ret
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%1 = getelementptr inbounds <4 x float>* %pb, i64 %index
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%2 = load <4 x float>* %1, align 16
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%3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
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ret <4 x float> %3
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}
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define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
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; CHECK-LABEL: insertps_from_broadcast_loadf32:
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; On X32, account for the arguments' move to registers
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; X32: movl 8(%esp), %eax
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; X32: movl 4(%esp), %ecx
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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%1 = getelementptr inbounds float* %fb, i64 %index
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%2 = load float* %1, align 4
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%3 = insertelement <4 x float> undef, float %2, i32 0
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%4 = insertelement <4 x float> %3, float %2, i32 1
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%5 = insertelement <4 x float> %4, float %2, i32 2
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%6 = insertelement <4 x float> %5, float %2, i32 3
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%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
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ret <4 x float> %7
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}
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define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
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; CHECK-LABEL: insertps_from_broadcast_loadv4f32:
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; On X32, account for the arguments' move to registers
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; X32: movl 4(%esp), %{{...}}
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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%1 = load <4 x float>* %b, align 4
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%2 = extractelement <4 x float> %1, i32 0
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%3 = insertelement <4 x float> undef, float %2, i32 0
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%4 = insertelement <4 x float> %3, float %2, i32 1
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%5 = insertelement <4 x float> %4, float %2, i32 2
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%6 = insertelement <4 x float> %5, float %2, i32 3
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%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
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ret <4 x float> %7
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}
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;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
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define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
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; CHECK-LABEL: insertps_from_broadcast_multiple_use:
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; On X32, account for the arguments' move to registers
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; X32: movl 8(%esp), %eax
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; X32: movl 4(%esp), %ecx
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; CHECK: vbroadcastss
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: vaddps
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; CHECK: vaddps
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; CHECK: vaddps
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; CHECK-NEXT: ret
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%1 = getelementptr inbounds float* %fb, i64 %index
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%2 = load float* %1, align 4
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%3 = insertelement <4 x float> undef, float %2, i32 0
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%4 = insertelement <4 x float> %3, float %2, i32 1
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%5 = insertelement <4 x float> %4, float %2, i32 2
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%6 = insertelement <4 x float> %5, float %2, i32 3
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%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
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%8 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %b, <4 x float> %6, i32 48)
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%9 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %c, <4 x float> %6, i32 48)
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%10 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %d, <4 x float> %6, i32 48)
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%11 = fadd <4 x float> %7, %8
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%12 = fadd <4 x float> %9, %10
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%13 = fadd <4 x float> %11, %12
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ret <4 x float> %13
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}
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