mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
9836c47ea6
Added target specific combine rules to fold blend intrinsics according to the following rules: 1) fold(blend A, A, Mask) -> A; 2) fold(blend A, B, <allZeros>) -> A; 3) fold(blend A, B, <allOnes>) -> B. Added two new tests to verify that the new folding rules work for all the optimized blend intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208895 91177308-0d34-0410-b5e6-96231b3b80d8
165 lines
5.4 KiB
LLVM
165 lines
5.4 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s
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; Verify that the backend correctly combines AVX2 builtin intrinsics.
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define <8 x i32> @test_psra_1(<8 x i32> %A) {
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %A, i32 3)
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%2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %1, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)
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%3 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %2, i32 2)
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ret <8 x i32> %3
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}
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; CHECK-LABEL: test_psra_1
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; CHECK: vpsrad $8, %ymm0, %ymm0
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; CHECK-NEXT: ret
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define <16 x i16> @test_psra_2(<16 x i16> %A) {
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%1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %A, i32 3)
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%2 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %1, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
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%3 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %2, i32 2)
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ret <16 x i16> %3
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}
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; CHECK-LABEL: test_psra_2
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; CHECK: vpsraw $8, %ymm0, %ymm0
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; CHECK-NEXT: ret
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define <16 x i16> @test_psra_3(<16 x i16> %A) {
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%1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %A, i32 0)
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%2 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
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%3 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %2, i32 0)
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ret <16 x i16> %3
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}
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; CHECK-LABEL: test_psra_3
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; CHECK-NOT: vpsraw
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; CHECK: ret
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define <8 x i32> @test_psra_4(<8 x i32> %A) {
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %A, i32 0)
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%2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)
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%3 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %2, i32 0)
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ret <8 x i32> %3
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}
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; CHECK-LABEL: test_psra_4
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; CHECK-NOT: vpsrad
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; CHECK: ret
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define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1) {
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%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a0, <32 x i8> %a1)
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ret <32 x i8> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendvb
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; CHECK-NOT: vpblendvb
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; CHECK: ret
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define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a0, i32 7)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a0, i32 7)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a0, i32 7)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <32 x i8> @test2_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1) {
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%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> zeroinitializer)
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ret <32 x i8> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendvb
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; CHECK-NOT: vpblendvb
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; CHECK: ret
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define <16 x i16> @test2_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 0)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test2_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 0)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test2_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 0)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <32 x i8> @test3_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1) {
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%1 = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <32 x i8>
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%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %1)
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ret <32 x i8> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendvb
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; CHECK-NOT: vpblendvb
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; CHECK: ret
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define <16 x i16> @test3_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 -1)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test3_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 -1)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test3_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 -1)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>)
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declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32)
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declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32)
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declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32)
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declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>)
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declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32)
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declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>)
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declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32)
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