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https://github.com/c64scene-ar/llvm-6502.git
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ff7e4b11b1
This effectively backs out r197465 but leaves some of the general fixes in place. Not all targets are ready to handle this feature. To enable it, some infrastructure work is needed to better handle register class constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197514 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.1 KiB
LLVM
44 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=generic | FileCheck %s
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; XFAIL: *
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; rdar:15661073 simple example of redundant adds
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;
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; MachineCSE should coalesce trivial subregister copies.
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;
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; The extra movl+addl should be removed during MachineCSE.
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; CHECK-LABEL: redundantadd
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; CHECK: cmpq
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; CHECK: movq
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; CHECK-NOT: movl
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; CHECK: addl
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; CHECK-NOT: addl
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; CHECK: ret
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define i64 @redundantadd(i64* %a0, i64* %a1) {
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entry:
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%tmp8 = load i64* %a0, align 8
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%tmp12 = load i64* %a1, align 8
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%tmp13 = icmp ult i64 %tmp12, -281474976710656
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br i1 %tmp13, label %exit1, label %body
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exit1:
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unreachable
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body:
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%tmp14 = trunc i64 %tmp8 to i32
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%tmp15 = trunc i64 %tmp12 to i32
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%tmp16 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %tmp14, i32 %tmp15)
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%tmp17 = extractvalue { i32, i1 } %tmp16, 1
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br i1 %tmp17, label %exit2, label %return
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exit2:
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unreachable
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return:
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%tmp18 = add i64 %tmp12, %tmp8
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%tmp19 = and i64 %tmp18, 4294967295
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%tmp20 = or i64 %tmp19, -281474976710656
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ret i64 %tmp20
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}
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
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