mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fb1293fd4c
of normally binary shuffle instructions like PUNPCKL and MOVLHPS. This detects cases where a single register is used for both operands making the shuffle behave in a unary way. We detect this and adjust the mask to use the unary form which allows the existing DAG combine for shuffle instructions to actually work at all. As a consequence, this uncovered a number of obvious bugs in the existing DAG combine which are fixed. It also now canonicalizes several shuffles even with the existing lowering. These typically are trying to match the shuffle to the domain of the input where before we only really modeled them with the floating point variants. All of the cases which change to an integer shuffle here have something in the integer domain, so there are no more or fewer domain crosses here AFAICT. Technically, it might be better to go from a GPR directly to the floating point domain, but detecting floating point *outputs* despite integer inputs is a lot more code and seems unlikely to be worthwhile in practice. If folks are seeing domain-crossing regressions here though, let me know and I can hack something up to fix it. Also as a consequence, a bunch of missed opportunities to form pshufb now can be formed. Notably, splats of i8s now form pshufb. Interestingly, this improves the existing splat lowering too. We go from 3 instructions to 1. Yes, we may tie up a register, but it seems very likely to be worth it, especially if splatting the 0th byte (the common case) as then we can use a zeroed register as the mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214625 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
5.2 KiB
LLVM
129 lines
5.2 KiB
LLVM
; RUN: llc -O3 -mtriple=x86_64-apple-macosx -o - < %s -mattr=+avx2 -enable-unsafe-fp-math -mcpu=core2 | FileCheck %s
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; Check that the ExeDepsFix pass correctly fixes the domain for broadcast instructions.
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; <rdar://problem/16354675>
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; CHECK-LABEL: ExeDepsFix_broadcastss
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; CHECK: broadcastss
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; CHECK: vandps
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; CHECK: vmaxps
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; CHECK: ret
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define <4 x float> @ExeDepsFix_broadcastss(<4 x float> %arg, <4 x float> %arg2) {
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%bitcast = bitcast <4 x float> %arg to <4 x i32>
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%and = and <4 x i32> %bitcast, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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%floatcast = bitcast <4 x i32> %and to <4 x float>
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%max_is_x = fcmp oge <4 x float> %floatcast, %arg2
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%max = select <4 x i1> %max_is_x, <4 x float> %floatcast, <4 x float> %arg2
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ret <4 x float> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastss256
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; CHECK: broadcastss
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; CHECK: vandps
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; CHECK: vmaxps
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; CHECK: ret
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define <8 x float> @ExeDepsFix_broadcastss256(<8 x float> %arg, <8 x float> %arg2) {
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%bitcast = bitcast <8 x float> %arg to <8 x i32>
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%and = and <8 x i32> %bitcast, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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%floatcast = bitcast <8 x i32> %and to <8 x float>
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%max_is_x = fcmp oge <8 x float> %floatcast, %arg2
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%max = select <8 x i1> %max_is_x, <8 x float> %floatcast, <8 x float> %arg2
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ret <8 x float> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastss_inreg
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; CHECK: broadcastss
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; CHECK: vandps
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; CHECK: vmaxps
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; CHECK: ret
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define <4 x float> @ExeDepsFix_broadcastss_inreg(<4 x float> %arg, <4 x float> %arg2, i32 %broadcastvalue) {
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%bitcast = bitcast <4 x float> %arg to <4 x i32>
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%in = insertelement <4 x i32> undef, i32 %broadcastvalue, i32 0
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%mask = shufflevector <4 x i32> %in, <4 x i32> undef, <4 x i32> zeroinitializer
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%and = and <4 x i32> %bitcast, %mask
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%floatcast = bitcast <4 x i32> %and to <4 x float>
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%max_is_x = fcmp oge <4 x float> %floatcast, %arg2
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%max = select <4 x i1> %max_is_x, <4 x float> %floatcast, <4 x float> %arg2
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ret <4 x float> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastss256_inreg
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; CHECK: broadcastss
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; CHECK: vandps
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; CHECK: vmaxps
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; CHECK: ret
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define <8 x float> @ExeDepsFix_broadcastss256_inreg(<8 x float> %arg, <8 x float> %arg2, i32 %broadcastvalue) {
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%bitcast = bitcast <8 x float> %arg to <8 x i32>
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%in = insertelement <8 x i32> undef, i32 %broadcastvalue, i32 0
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%mask = shufflevector <8 x i32> %in, <8 x i32> undef, <8 x i32> zeroinitializer
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%and = and <8 x i32> %bitcast, %mask
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%floatcast = bitcast <8 x i32> %and to <8 x float>
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%max_is_x = fcmp oge <8 x float> %floatcast, %arg2
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%max = select <8 x i1> %max_is_x, <8 x float> %floatcast, <8 x float> %arg2
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ret <8 x float> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastsd
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; In that case the broadcast is directly folded into vandpd.
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; CHECK: vandpd
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; CHECK: vmaxpd
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; CHECK:ret
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define <2 x double> @ExeDepsFix_broadcastsd(<2 x double> %arg, <2 x double> %arg2) {
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%bitcast = bitcast <2 x double> %arg to <2 x i64>
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%and = and <2 x i64> %bitcast, <i64 2147483647, i64 2147483647>
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%floatcast = bitcast <2 x i64> %and to <2 x double>
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%max_is_x = fcmp oge <2 x double> %floatcast, %arg2
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%max = select <2 x i1> %max_is_x, <2 x double> %floatcast, <2 x double> %arg2
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ret <2 x double> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastsd256
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; CHECK: broadcastsd
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; CHECK: vandpd
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; CHECK: vmaxpd
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; CHECK: ret
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define <4 x double> @ExeDepsFix_broadcastsd256(<4 x double> %arg, <4 x double> %arg2) {
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%bitcast = bitcast <4 x double> %arg to <4 x i64>
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%and = and <4 x i64> %bitcast, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
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%floatcast = bitcast <4 x i64> %and to <4 x double>
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%max_is_x = fcmp oge <4 x double> %floatcast, %arg2
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%max = select <4 x i1> %max_is_x, <4 x double> %floatcast, <4 x double> %arg2
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ret <4 x double> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastsd_inreg
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; ExeDepsFix works top down, thus it coalesces vpunpcklqdq domain with
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; vpand and there is nothing more you can do to match vmaxpd.
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; CHECK: vpunpcklqdq
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; CHECK: vpand
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; CHECK: vmaxpd
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; CHECK: ret
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define <2 x double> @ExeDepsFix_broadcastsd_inreg(<2 x double> %arg, <2 x double> %arg2, i64 %broadcastvalue) {
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%bitcast = bitcast <2 x double> %arg to <2 x i64>
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%in = insertelement <2 x i64> undef, i64 %broadcastvalue, i32 0
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%mask = shufflevector <2 x i64> %in, <2 x i64> undef, <2 x i32> zeroinitializer
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%and = and <2 x i64> %bitcast, %mask
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%floatcast = bitcast <2 x i64> %and to <2 x double>
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%max_is_x = fcmp oge <2 x double> %floatcast, %arg2
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%max = select <2 x i1> %max_is_x, <2 x double> %floatcast, <2 x double> %arg2
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ret <2 x double> %max
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}
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; CHECK-LABEL: ExeDepsFix_broadcastsd256_inreg
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; CHECK: broadcastsd
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; CHECK: vandpd
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; CHECK: vmaxpd
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; CHECK: ret
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define <4 x double> @ExeDepsFix_broadcastsd256_inreg(<4 x double> %arg, <4 x double> %arg2, i64 %broadcastvalue) {
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%bitcast = bitcast <4 x double> %arg to <4 x i64>
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%in = insertelement <4 x i64> undef, i64 %broadcastvalue, i32 0
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%mask = shufflevector <4 x i64> %in, <4 x i64> undef, <4 x i32> zeroinitializer
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%and = and <4 x i64> %bitcast, %mask
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%floatcast = bitcast <4 x i64> %and to <4 x double>
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%max_is_x = fcmp oge <4 x double> %floatcast, %arg2
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%max = select <4 x i1> %max_is_x, <4 x double> %floatcast, <4 x double> %arg2
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ret <4 x double> %max
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}
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