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https://github.com/c64scene-ar/llvm-6502.git
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6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.4 KiB
LLVM
60 lines
1.4 KiB
LLVM
; An integer truncation to i1 should be done with an and instruction to make
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; sure only the LSBit survives. Test that this is the case both for a returned
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; value and as the operand of a branch.
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; RUN: llc < %s -march=x86 | FileCheck %s
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define zeroext i1 @test1(i32 %X) nounwind {
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%Y = trunc i32 %X to i1
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ret i1 %Y
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}
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; CHECK-LABEL: test1:
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; CHECK: andl $1, %eax
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define i1 @test2(i32 %val, i32 %mask) nounwind {
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entry:
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%shifted = ashr i32 %val, %mask
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%anded = and i32 %shifted, 1
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%trunced = trunc i32 %anded to i1
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br i1 %trunced, label %ret_true, label %ret_false
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ret_true:
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ret i1 true
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ret_false:
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ret i1 false
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}
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; CHECK-LABEL: test2:
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; CHECK: btl
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define i32 @test3(i8* %ptr) nounwind {
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%val = load i8* %ptr
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%tmp = trunc i8 %val to i1
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br i1 %tmp, label %cond_true, label %cond_false
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cond_true:
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ret i32 21
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cond_false:
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ret i32 42
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}
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; CHECK-LABEL: test3:
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; CHECK: testb $1, (%eax)
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define i32 @test4(i8* %ptr) nounwind {
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%tmp = ptrtoint i8* %ptr to i1
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br i1 %tmp, label %cond_true, label %cond_false
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cond_true:
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ret i32 21
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cond_false:
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ret i32 42
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}
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; CHECK-LABEL: test4:
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; CHECK: testb $1, 4(%esp)
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define i32 @test5(double %d) nounwind {
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%tmp = fptosi double %d to i1
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br i1 %tmp, label %cond_true, label %cond_false
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cond_true:
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ret i32 21
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cond_false:
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ret i32 42
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}
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; CHECK-LABEL: test5:
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; CHECK: testb $1
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