mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
7e3dc40fab
we stopped efficiently lowering sextload using the SSE41 instructions for that operation. This is a consequence of a bad predicate I used thinking of the memory access needs. The code actually handles the cases where the predicate doesn't apply, and handles them much better. =] Simple fix and a test case added. Fixes PR20767. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216538 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
2.0 KiB
LLVM
81 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
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define<4 x i32> @func_16_32() {
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%F = load <4 x i16>* undef
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%G = sext <4 x i16> %F to <4 x i32>
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%H = load <4 x i16>* undef
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%Y = sext <4 x i16> %H to <4 x i32>
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%T = add <4 x i32> %Y, %G
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store <4 x i32>%T , <4 x i32>* undef
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ret <4 x i32> %T
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}
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define<4 x i64> @func_16_64() {
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%F = load <4 x i16>* undef
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%G = sext <4 x i16> %F to <4 x i64>
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%H = load <4 x i16>* undef
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%Y = sext <4 x i16> %H to <4 x i64>
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%T = xor <4 x i64> %Y, %G
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store <4 x i64>%T , <4 x i64>* undef
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ret <4 x i64> %T
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}
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define<4 x i64> @func_32_64() {
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%F = load <4 x i32>* undef
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%G = sext <4 x i32> %F to <4 x i64>
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%H = load <4 x i32>* undef
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%Y = sext <4 x i32> %H to <4 x i64>
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%T = or <4 x i64> %Y, %G
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ret <4 x i64> %T
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}
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define<4 x i16> @func_8_16() {
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%F = load <4 x i8>* undef
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%G = sext <4 x i8> %F to <4 x i16>
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%H = load <4 x i8>* undef
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%Y = sext <4 x i8> %H to <4 x i16>
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%T = add <4 x i16> %Y, %G
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ret <4 x i16> %T
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}
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define<4 x i32> @func_8_32() {
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%F = load <4 x i8>* undef
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%G = sext <4 x i8> %F to <4 x i32>
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%H = load <4 x i8>* undef
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%Y = sext <4 x i8> %H to <4 x i32>
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%T = sub <4 x i32> %Y, %G
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ret <4 x i32> %T
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}
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define<4 x i64> @func_8_64() {
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%F = load <4 x i8>* undef
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%G = sext <4 x i8> %F to <4 x i64>
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%H = load <4 x i8>* undef
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%Y = sext <4 x i8> %H to <4 x i64>
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%T = add <4 x i64> %Y, %G
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ret <4 x i64> %T
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}
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define<4 x i32> @const_16_32() {
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%G = sext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32>
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ret <4 x i32> %G
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}
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define<4 x i64> @const_16_64() {
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%G = sext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64>
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ret <4 x i64> %G
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}
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define <4 x i32> @sextload(<4 x i16>* %ptr) {
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; From PR20767 - make sure that we correctly use SSE4.1 to do sign extension
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; loads for both 32-bit and 64-bit x86 targets.
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; CHECK-LABEL: sextload:
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; CHECK: vpmovsxwd {{.*}}, %xmm0
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; CHECK-NEXT: ret
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entry:
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%l = load<4 x i16>* %ptr
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%m = sext<4 x i16> %l to <4 x i32>
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ret <4 x i32> %m
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}
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