llvm-6502/test/CodeGen/X86/vec_shuffle-36.ll
Rafael Espindola 7cb1b5f5bf Replace more uses of sse41 with sse4.1.
llc using the host cpu features and *waning* on unknown features is probably
not a good thing :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:39:19 +00:00

17 lines
576 B
LLVM

; RUN: llc < %s -march=x86-64 -mcpu=penryn -mattr=sse4.1 | FileCheck %s
define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
; CHECK: pshufb
; CHECK-NOT: pshufb
; CHECK: ret
entry:
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 2, i32 0, i32 2, i32 1, i32 5, i32 6 , i32 undef >
ret <8 x i16> %tmp9
}
define <8 x i16> @shuf7(<8 x i16> %t0) {
; CHECK: pshufd
%tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef >
ret <8 x i16> %tmp10
}