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llvm-6502/test/CodeGen
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NAKAMURA Takumi 9160c024b9 llvm/test/CodeGen/X86/xor.ll: Appease Win32 targets since r240796. 
%struct.ref_s = type { %union.v, i16, i16 }
  %union.v = type { i64 }

It seems %struct.ref_s is incompatible in tail padding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240874 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 03:46:58 +00:00
..
AArch64 [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses. 2015-06-26 02:32:07 +00:00
AMDGPU AMDPGU/SI: Use correct resource descriptors for VI on HSA 2015-06-26 21:58:42 +00:00
ARM [ARM] Cortex-R5 is not VFPOnlySP 2015-06-26 17:42:37 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips Fix "the the" in comments. 2015-06-19 01:53:21 +00:00
MIR MIR Serialization: Serialize global address machine operands. 2015-06-26 22:56:48 +00:00
MSP430
NVPTX [NVPTX] noop when kernel pointers are already global 2015-06-26 22:35:43 +00:00
PowerPC Add missing builtins to the PPC back end for ABI compliance (vol. 1) 2015-06-26 19:26:53 +00:00
SPARC Revert r240302 ("Bring r240130 back."). 2015-06-23 11:31:32 +00:00
SystemZ
Thumb
Thumb2 ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it 2015-06-24 20:03:27 +00:00
WinEH [Verifier] Verify invokes of intrinsics 2015-06-26 21:39:44 +00:00
X86 llvm/test/CodeGen/X86/xor.ll: Appease Win32 targets since r240796. 2015-06-27 03:46:58 +00:00
XCore