Jim Grosbach 860122b3b7 X86: Don't over-align combined loads. ... When combining consecutive loads+inserts into a single vector load, we should keep the alignment of the base load. Doing otherwise can, and does, lead to using overly aligned instructions. In the included test case, for example, using a 32-byte vmovaps on a 16-byte aligned value. Oops. rdar://19190968 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224746 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-23 00:35:23 +00:00
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AArch64	Lower multiply-negate operation to mneg on AArch64	2014-12-22 13:38:58 +00:00
ARM	Convert a few tests to FileCheck. NFC.	2014-12-22 13:29:46 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.	2014-12-22 21:40:43 +00:00
Inputs
Mips	[mips][microMIPS] Fix bugs related to atomic SC/LL instructions	2014-12-18 16:39:29 +00:00
MSP430
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC
R600	Enable (sext x) == C --> x == (trunc C) combine	2014-12-21 16:48:42 +00:00
SPARC
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X86	X86: Don't over-align combined loads.	2014-12-23 00:35:23 +00:00
XCore