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isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
4.6 KiB
C++
127 lines
4.6 KiB
C++
//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfoImpl class, it just provides default
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// implementations of various methods.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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// commuteInstruction - The default implementation of this method just exchanges
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// operand 1 and 2.
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MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool ChangeReg0 = false;
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if (MI->getOperand(0).getReg() == Reg1) {
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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ChangeReg0 = true;
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}
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
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bool Reg0IsDead = MI->getOperand(0).isDead();
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MachineFunction &MF = *MI->getParent()->getParent();
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return BuildMI(MF, MI->getDesc())
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.addReg(Reg0, true, false, false, Reg0IsDead)
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.addReg(Reg2, false, false, Reg2IsKill)
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.addReg(Reg1, false, false, Reg1IsKill);
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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return MI;
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}
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/// CommuteChangesDestination - Return true if commuting the specified
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/// instruction will also changes the destination operand. Also return the
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/// current operand index of the would be new destination register by
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/// reference. This can happen when the commutable instruction is also a
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/// two-address instruction.
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bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
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unsigned &OpIdx) const{
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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"This only knows how to commute register operands so far");
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if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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OpIdx = 2;
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return true;
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}
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return false;
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}
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bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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bool MadeChange = false;
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isPredicable())
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return false;
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (TID.OpInfo[i].isPredicate()) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister()) {
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MO.setReg(Pred[j].getReg());
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MadeChange = true;
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} else if (MO.isImmediate()) {
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MO.setImm(Pred[j].getImm());
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MadeChange = true;
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} else if (MO.isMachineBasicBlock()) {
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MO.setMBB(Pred[j].getMBB());
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MadeChange = true;
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}
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++j;
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}
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}
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return MadeChange;
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}
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void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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unsigned
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TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
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unsigned FnSize = 0;
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for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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const MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
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I != E; ++I)
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FnSize += GetInstSizeInBytes(I);
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}
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return FnSize;
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}
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