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https://github.com/c64scene-ar/llvm-6502.git
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8a8d479214
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.6 KiB
C++
97 lines
3.6 KiB
C++
//===- CodeGen/Analysis.h - CodeGen LLVM IR Analysis Utilities --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares several CodeGen-specific LLVM IR analysis utilties.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_ANALYSIS_H
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#define LLVM_CODEGEN_ANALYSIS_H
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#include "llvm/Instructions.h"
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#include "llvm/InlineAsm.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/Support/CallSite.h"
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namespace llvm {
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class GlobalVariable;
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class TargetLowering;
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class SDNode;
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class SelectionDAG;
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/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
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/// of insertvalue or extractvalue indices that identify a member, return
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/// the linearized index of the start of the member.
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///
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unsigned ComputeLinearIndex(Type *Ty,
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const unsigned *Indices,
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const unsigned *IndicesEnd,
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unsigned CurIndex = 0);
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inline unsigned ComputeLinearIndex(Type *Ty,
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ArrayRef<unsigned> Indices,
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unsigned CurIndex = 0) {
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return ComputeLinearIndex(Ty, Indices.begin(), Indices.end(), CurIndex);
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}
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/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
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/// EVTs that represent all the individual underlying
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/// non-aggregate types that comprise it.
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///
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/// If Offsets is non-null, it points to a vector to be filled in
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/// with the in-memory offsets of each of the individual values.
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///
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void ComputeValueVTs(const TargetLowering &TLI, Type *Ty,
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SmallVectorImpl<EVT> &ValueVTs,
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SmallVectorImpl<uint64_t> *Offsets = 0,
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uint64_t StartingOffset = 0);
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/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
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GlobalVariable *ExtractTypeInfo(Value *V);
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/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
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/// processed uses a memory 'm' constraint.
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bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
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const TargetLowering &TLI);
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/// getFCmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR floating-point condition code. This includes
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/// consideration of global floating-point math flags.
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///
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ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
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/// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
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/// return the equivalent code if we're allowed to assume that NaNs won't occur.
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ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
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/// getICmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR integer condition code.
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///
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ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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/// Test if the given instruction is in a position to be optimized
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/// with a tail-call. This roughly means that it's in a block with
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/// a return and there's nothing that needs to be scheduled
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/// between it and the return.
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///
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/// This function only tests target-independent requirements.
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bool isInTailCallPosition(ImmutableCallSite CS, Attributes CalleeRetAttr,
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const TargetLowering &TLI);
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bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
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const TargetLowering &TLI);
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} // End llvm namespace
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#endif
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