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eca517deaa
for the Sparc port. Use the same initializeSubtargetDependencies function to handle initialization similar to the other ports to handle dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211811 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.8 KiB
C++
84 lines
2.8 KiB
C++
//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Sparc specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCTARGETMACHINE_H
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#define SPARCTARGETMACHINE_H
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#include "SparcInstrInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class SparcTargetMachine : public LLVMTargetMachine {
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SparcSubtarget Subtarget;
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public:
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SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64bit);
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const SparcInstrInfo *getInstrInfo() const override {
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return getSubtargetImpl()->getInstrInfo();
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}
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const TargetFrameLowering *getFrameLowering() const override {
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return getSubtargetImpl()->getFrameLowering();
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}
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const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
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const SparcRegisterInfo *getRegisterInfo() const override {
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return getSubtargetImpl()->getRegisterInfo();
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}
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const SparcTargetLowering *getTargetLowering() const override {
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return getSubtargetImpl()->getTargetLowering();
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}
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const SparcSelectionDAGInfo *getSelectionDAGInfo() const override {
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return getSubtargetImpl()->getSelectionDAGInfo();
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}
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SparcJITInfo *getJITInfo() override { return Subtarget.getJITInfo(); }
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const DataLayout *getDataLayout() const override {
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return getSubtargetImpl()->getDataLayout();
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}
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
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};
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/// SparcV8TargetMachine - Sparc 32-bit target machine
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///
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class SparcV8TargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcV8TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// SparcV9TargetMachine - Sparc 64-bit target machine
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///
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class SparcV9TargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcV9TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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