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6fac1fbf30
This pattern occurs in SROA output due to the way vector arguments are lowered
on ARM.
The testcase from PR15525 now compiles into this, which is better than the code
we got with the old scalarrepl:
_Store:
ldr.w r9, [sp]
vmov d17, r3, r9
vmov d16, r1, r2
vst1.8 {d16, d17}, [r0]
bx lr
Differential Revision: http://llvm-reviews.chandlerc.com/D647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179106 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
1.3 KiB
LLVM
24 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
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; PR15525
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; CHECK: test1:
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; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
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; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2
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; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
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; CHECK-NEXT: vst1.8 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0]
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; CHECK-NEXT: bx lr
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define void @test1(i8* %arg, [4 x i64] %vec.coerce) {
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bb:
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%tmp = extractvalue [4 x i64] %vec.coerce, 0
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%tmp2 = bitcast i64 %tmp to <8 x i8>
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%tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%tmp4 = extractvalue [4 x i64] %vec.coerce, 1
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%tmp5 = bitcast i64 %tmp4 to <8 x i8>
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%tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> %tmp3, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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tail call void @llvm.arm.neon.vst1.v16i8(i8* %arg, <16 x i8> %tmp7, i32 2)
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ret void
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}
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declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32)
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