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f961273b79
This makes lib/Target/PowerPC EmitRawText free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200065 91177308-0d34-0410-b5e6-96231b3b80d8
234 lines
8.6 KiB
C++
234 lines
8.6 KiB
C++
//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides PowerPC specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCMCTargetDesc.h"
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#include "InstPrinter/PPCInstPrinter.h"
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#include "PPCMCAsmInfo.h"
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#include "PPCTargetStreamer.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_MC_DESC
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#include "PPCGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "PPCGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "PPCGenRegisterInfo.inc"
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using namespace llvm;
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// Pin the vtable to this file.
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PPCTargetStreamer::~PPCTargetStreamer() {}
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static MCInstrInfo *createPPCMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitPPCMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
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Triple TheTriple(TT);
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bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
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TheTriple.getArch() == Triple::ppc64le);
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unsigned Flavour = isPPC64 ? 0 : 1;
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unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
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MCRegisterInfo *X = new MCRegisterInfo();
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InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
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return X;
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}
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static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitPPCMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
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Triple TheTriple(TT);
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bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
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TheTriple.getArch() == Triple::ppc64le);
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MCAsmInfo *MAI;
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if (TheTriple.isOSDarwin())
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MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
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else
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MAI = new PPCLinuxMCAsmInfo(isPPC64);
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// Initial state of the frame pointer is R1.
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unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
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MCCFIInstruction Inst =
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MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(Reg, true), 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (RM == Reloc::Default) {
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Triple T(TT);
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if (T.isOSDarwin())
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RM = Reloc::DynamicNoPIC;
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else
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RM = Reloc::Static;
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}
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if (CM == CodeModel::Default) {
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Triple T(TT);
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if (!T.isOSDarwin() &&
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(T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le))
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CM = CodeModel::Medium;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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namespace {
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class PPCTargetAsmStreamer : public PPCTargetStreamer {
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formatted_raw_ostream &OS;
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public:
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PPCTargetAsmStreamer(formatted_raw_ostream &OS) : OS(OS) {}
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virtual void emitTCEntry(const MCSymbol &S) {
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OS << "\t.tc ";
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OS << S.getName();
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OS << "[TC],";
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OS << S.getName();
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OS << '\n';
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}
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virtual void emitMachine(StringRef CPU) {
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OS << "\t.machine " << CPU << '\n';
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}
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};
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class PPCTargetELFStreamer : public PPCTargetStreamer {
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virtual void emitTCEntry(const MCSymbol &S) {
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// Creates a R_PPC64_TOC relocation
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Streamer->EmitSymbolValue(&S, 8);
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}
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virtual void emitMachine(StringRef CPU) {
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// FIXME: Is there anything to do in here or does this directive only
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// limit the parser?
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}
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};
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}
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// This is duplicated code. Refactor this.
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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bool RelaxAll,
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bool NoExecStack) {
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if (Triple(TT).isOSDarwin())
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return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
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PPCTargetStreamer *S = new PPCTargetELFStreamer();
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return createELFStreamer(Ctx, S, MAB, OS, Emitter, RelaxAll, NoExecStack);
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}
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static MCStreamer *
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createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
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bool isVerboseAsm, bool useLoc, bool useCFI,
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bool useDwarfDirectory, MCInstPrinter *InstPrint,
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MCCodeEmitter *CE, MCAsmBackend *TAB, bool ShowInst) {
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PPCTargetStreamer *S = new PPCTargetAsmStreamer(OS);
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return llvm::createAsmStreamer(Ctx, S, OS, isVerboseAsm, useLoc, useCFI,
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useDwarfDirectory, InstPrint, CE, TAB,
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ShowInst);
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}
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static MCInstPrinter *createPPCMCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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bool isDarwin = Triple(STI.getTargetTriple()).isOSDarwin();
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return new PPCInstPrinter(MAI, MII, MRI, isDarwin);
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}
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extern "C" void LLVMInitializePowerPCTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo);
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RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo);
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RegisterMCAsmInfoFn E(ThePPC64LETarget, createPPCMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(ThePPC32Target, createPPCMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(ThePPC64Target, createPPCMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(ThePPC64LETarget,
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createPPCMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(ThePPC64LETarget,
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createPPCMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(ThePPC32Target, createPPCMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(ThePPC64Target, createPPCMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(ThePPC64LETarget, createPPCMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
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createPPCMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
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createPPCMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(ThePPC64LETarget,
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createPPCMCSubtargetInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(ThePPC64LETarget,
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createPPCMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(ThePPC32Target, createPPCAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(ThePPC64Target, createPPCAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(ThePPC64LETarget, createPPCAsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterMCObjectStreamer(ThePPC32Target, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(ThePPC64Target, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(ThePPC64LETarget, createMCStreamer);
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// Register the asm streamer.
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TargetRegistry::RegisterAsmStreamer(ThePPC32Target, createMCAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(ThePPC64Target, createMCAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(ThePPC64LETarget, createMCAsmStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(ThePPC64Target, createPPCMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(ThePPC64LETarget,
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createPPCMCInstPrinter);
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}
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