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https://github.com/c64scene-ar/llvm-6502.git
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11addd2a2f
This patch adds fast-isel support for calls (but not intrinsic calls or varargs calls). It also removes a badly-formed assert. There are some new tests just for calls, and also for folding loads into arguments on calls to avoid extra extends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189701 91177308-0d34-0410-b5e6-96231b3b80d8
181 lines
7.8 KiB
TableGen
181 lines
7.8 KiB
TableGen
//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the PowerPC 32- and 64-bit
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// architectures.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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// Return-value convention for PowerPC
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def RetCC_PPC : CallingConv<[
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// On PPC64, integer return values are always promoted to i64
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CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
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CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
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// Vector types are always returned in V2.
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
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]>;
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// Note that we don't currently have calling conventions for 64-bit
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// PowerPC, but handle all the complexities of the ABI in the lowering
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// logic. FIXME: See if the logic can be simplified with use of CCs.
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// This may require some extensions to current table generation.
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// Simple calling convention for 64-bit ELF PowerPC fast isel.
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// Only handle ints and floats. All ints are promoted to i64.
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// Vector types and quadword ints are not handled.
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def CC_PPC64_ELF_FIS : CallingConv<[
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
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]>;
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// Simple return-value convention for 64-bit ELF PowerPC fast isel.
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// All small ints are promoted to i64. Vector types, quadword ints,
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// and multiple register returns are "supported" to avoid compile
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// errors, but none are handled by the fast selector.
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def RetCC_PPC64_ELF_FIS : CallingConv<[
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4]>>,
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CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
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CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
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]>;
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//===----------------------------------------------------------------------===//
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// PowerPC System V Release 4 32-bit ABI
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//===----------------------------------------------------------------------===//
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def CC_PPC32_SVR4_Common : CallingConv<[
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// The ABI requires i64 to be passed in two adjacent registers with the first
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// register having an odd register number.
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CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
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// The first 8 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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// Make sure the i64 words from a long double are either both passed in
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// registers or both passed on the stack.
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CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
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// FP values are passed in F1 - F8.
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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// Split arguments have an alignment of 8 bytes on the stack.
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CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
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CCIfType<[i32], CCAssignToStack<4, 4>>,
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// Floats are stored in double precision format, thus they have the same
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// alignment and size as doubles.
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CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
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]>;
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// This calling convention puts vector arguments always on the stack. It is used
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// to assign vector arguments which belong to the variable portion of the
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// parameter list of a variable argument function.
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def CC_PPC32_SVR4_VarArg : CallingConv<[
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CCDelegateTo<CC_PPC32_SVR4_Common>
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]>;
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// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
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// put vector arguments in vector registers before putting them on the stack.
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def CC_PPC32_SVR4 : CallingConv<[
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// The first 12 Vector arguments are passed in AltiVec registers.
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CCIfType<[v16i8, v8i16, v4i32, v4f32],
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
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CCDelegateTo<CC_PPC32_SVR4_Common>
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]>;
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// Helper "calling convention" to handle aggregate by value arguments.
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// Aggregate by value arguments are always placed in the local variable space
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// of the caller. This calling convention is only used to assign those stack
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// offsets in the callers stack frame.
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//
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// Still, the address of the aggregate copy in the callers stack frame is passed
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// in a GPR (or in the parameter list area if all GPRs are allocated) from the
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// caller to the callee. The location for the address argument is assigned by
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// the CC_PPC32_SVR4 calling convention.
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//
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// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
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// not passed by value.
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def CC_PPC32_SVR4_ByVal : CallingConv<[
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CCIfByVal<CCPassByVal<4, 4>>,
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CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
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]>;
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def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
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V28, V29, V30, V31)>;
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def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28,
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R29, R30, R31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
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def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28,
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R29, R30, R31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
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def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
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X21, X22, X23, X24, X25, X26, X27, X28,
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X29, X30, X31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
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def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
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X21, X22, X23, X24, X25, X26, X27, X28,
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X29, X30, X31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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