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https://github.com/c64scene-ar/llvm-6502.git
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The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
154 lines
4.0 KiB
ArmAsm
154 lines
4.0 KiB
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
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@ CHECK: nop
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@ CHECK: encoding: [0x00,0xf0,0x20,0xe3]
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nop
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@ CHECK: nopeq
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@ CHECK: encoding: [0x00,0xf0,0x20,0x03]
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nopeq
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@ CHECK: trap
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@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
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trap
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@ CHECK: bx lr
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@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
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bx lr
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@ CHECK: vqdmull.s32 q8, d17, d16
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@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
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vqdmull.s32 q8, d17, d16
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@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
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and r1,r2,r3
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@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
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ands r1,r2,r3
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@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
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eor r1,r2,r3
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@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
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eors r1,r2,r3
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@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
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sub r1,r2,r3
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@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
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subs r1,r2,r3
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@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
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add r1,r2,r3
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@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
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adds r1,r2,r3
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@ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
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adc r1,r2,r3
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@ CHECK: sbc r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0]
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sbc r1,r2,r3
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@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1]
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orr r1,r2,r3
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@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1]
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orrs r1,r2,r3
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@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
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bic r1,r2,r3
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@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
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bics r1,r2,r3
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@ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
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mov r1,r2
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@ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
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mvn r1,r2
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@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
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mvns r1,r2
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@ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0]
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rsb r1,r2,r3
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@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0]
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rsc r1,r2,r3
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@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7]
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bfi r0, r0, #5, #7
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@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
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bkpt #10
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@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
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cdp p7, #1, c1, c1, c1, #4
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@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
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cdp2 p7, #1, c1, c1, c1, #4
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@ CHECK: qadd r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1]
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qadd r1, r2, r3
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@ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
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qsub r1, r2, r3
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@ CHECK: qdadd r1, r2, r3 @ encoding: [0x52,0x10,0x43,0xe1]
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qdadd r1, r2, r3
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@ CHECK: qdsub r1, r2, r3 @ encoding: [0x52,0x10,0x63,0xe1]
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qdsub r1, r2, r3
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@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
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wfe
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@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
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wfi
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@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
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yield
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@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
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nop
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@ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1]
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cpsie aif
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@ CHECK: cps #15 @ encoding: [0x0f,0x00,0x02,0xf1]
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cps #15
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@ CHECK: cpsie if, #10 @ encoding: [0xca,0x00,0x0a,0xf1]
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cpsie if, #10
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@ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0]
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add r1, r2, r3, lsl r4
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@ CHECK: strexb r0, r1, [r2] @ encoding: [0x91,0x0f,0xc2,0xe1]
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strexb r0, r1, [r2]
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@ CHECK: strexh r0, r1, [r2] @ encoding: [0x91,0x0f,0xe2,0xe1]
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strexh r0, r1, [r2]
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@ CHECK: strex r0, r1, [r2] @ encoding: [0x91,0x0f,0x82,0xe1]
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strex r0, r1, [r2]
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@ CHECK: strexd r0, r2, r3, [r1] @ encoding: [0x92,0x0f,0xa1,0xe1]
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strexd r0, r2, r3, [r1]
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@ CHECK: ldrexb r0, [r0] @ encoding: [0x9f,0x0f,0xd0,0xe1]
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ldrexb r0, [r0]
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@ CHECK: ldrexh r0, [r0] @ encoding: [0x9f,0x0f,0xf0,0xe1]
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ldrexh r0, [r0]
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@ CHECK: ldrex r0, [r0] @ encoding: [0x9f,0x0f,0x90,0xe1]
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ldrex r0, [r0]
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@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
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ldrexd r0, r1, [r0]
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@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6]
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ssat16 r0, #7, r0
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