llvm-6502/test/CodeGen
Oliver Stannard b1d8e7e77c [ARM] Select VMAXNM and VMINNM regardless of operand order
Currently, the ARM backend will select the VMAXNM and VMINNM for these C
expressions:
  (a < b) ? a : b
  (a > b) ? a : b
but not these expressions:
  (a > b) ? b : a
  (a < b) ? b : a

This patch allows all of these expressions to be matched.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-27 09:23:02 +00:00
..
AArch64 [AArch64] Fix fast-isel of cbz of i1, i8, i16 2014-10-24 09:54:41 +00:00
ARM [ARM] Select VMAXNM and VMINNM regardless of operand order 2014-10-27 09:23:02 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips] For N32/N64, structs must be passed in the upper bits of a register. 2014-10-24 13:09:19 +00:00
MSP430
NVPTX [NVPTX] aligned byte-buffers for vector return types 2014-10-25 03:46:16 +00:00
PowerPC [PATCH] Support select-cc for VSFRC when VSX is enabled 2014-10-22 16:58:20 +00:00
R600 R600/SI: Add another failing testcase for i1 copies 2014-10-22 05:30:42 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [X86][SSE] Bitcast assertion in XFormVExtractWithShuffleIntoLoad 2014-10-24 21:04:41 +00:00
XCore Fix a bit of confusion about .set and produce more readable assembly. 2014-10-21 01:17:30 +00:00